DOWNLOAD Sharp PZ-50MR2E (serv.man10) Service Manual ↓ Size: 1.18 MB | Pages: 7 in PDF or view online for FREE

Model
PZ-50MR2E (serv.man10)
Pages
7
Size
1.18 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD / Block diagram
File
pz-50mr2e-sm10.pdf
Date

Sharp PZ-50MR2E (serv.man10) Service Manual ▷ View online

59
58
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
PZ-43MR2E
PZ-50MR2E
POWER BLOCK DIAGRAM
61
60
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
PZ-43MR2E
PZ-50MR2E
PC I/F BLOCK DIAGRAM
V0
A/D
Amp
PLL
IC4
CXA3506R
I
2
C=CH2
5V->3.3V
Reg
IC8 PQ2 0VZ11
X5
79.794MHz
DO_VS YNC
DO_HS YNC
LCLK(79.79 4MHz)
X4
25MHz
EEPROM
IC3
AT24C1 28N
I
2
C=CH3
CVIC
IC25
V1
A/D
IC310
TLC57 33A
12V->5VReg
IC7 PQ0 5TZ11
TMDS(4ch)
PanelLink
HDCP
Transmitter
IC413
SiI168
I
2
C=CH1
CPU
IC1
SH7709
I
2
C
 PORT
CH1 Do:PTB4,Di:PTG5,Clk:PT B5
CH2 Do:PTC1,Di:PTF2,Clk:PTC2
CH3 Do:PTA6,Di:PTG6,Clk:PTA7
CH4 Do:PTD0,Di:PTG4,Clk:PTA4
PC_ C3
HV SEL
OV0 _H
V1
PLL
IC328
TLC 2933IPW
12V->9V R eg
IC415 B A09FP
OV0_CLP
5V->3.3V R eg
IC412 PQ1 R33
DO_HD ISP
EEPROM
IC414
M24C32
X3
1.8432MHz
-RESET_C1
-
RST_P LL
-C1_I NT
CPCI-00 56CE
XPWR_SV
-CS2
-WAIT _C1
V0
Sync
Sel
IC411
74LCX157
1B
2B
4B
1A
2A
4A
-A /+B
1Y
2Y
4Y
CN
8
7
9
10
PC _H
P C_V
P C_C
CN
6
18
17
29,3
0
MAIN _H
D
MAIN_VD
5
1
3
P C_R
RIN2
GIN2
BIN2
PC _G
P C_B
RIN1
GIN1
BIN1
25,2
6
21,2
2
MAI N_
B
MAI N_
G
MAI N_
R
ROUT
GOUT
BOUT
SYNCIN1
SYNCIN2
HOLD
CLPIN
DIVOUT
1/2C LK
XPOWERSAVE
RA[7..0]
RB[7..0]
GA[7..0]
GB[7..0]
BA[7..0]
BB[7. .0]
AIN
BIN
CIN
RT
RB
3.27V
1.17V
AO[8..1]
BO[8..1]
CO[8..1]
EXTCLP
CLK
- OE
FIN-A
FIN-B
PFDINH
VCOOUT
13,1
4
9,10
5,6
SUB _Y
SUB_ Cb
SUB_ Cr
SUB_
HD
2
1
SUB
_VD
About 60MHz
12pin  TO CONNECTOR PWB
SDRAM
512Kx128bitx4 BANK
8
V0_HSYNC
V0_VSYNC
V0_CSYNC
OV0_V
V0_HSYNR
OV0_HSYNR
V0_PDEN
OV0_PDEN
V0_CLP
OV0_CLP
V0_HSYNC2
V0_VDCLK_I
OV0_HSC2
OVCLK(Max60MHz)
V0_RA[7..0]
V0_RB[7..0]
V0_GA[7..0]
V0_GB[7..0]
V0_BA[7..0]
V0_BB[7..0]
8
8
8
8
8
XPW R_SV
V1_GA[7..0]
V1_BA[7..0]
V1_RA[7..0]
8
8
8
OV1_VCKO
(
15M Hz)
V1_VDCLK_O
OV1_CLP
V1_CLP
SAD C_OE
V1_HSYNR
V1_HSYNF
V1_PDEN
OV1_HSNR
OV1_HSNF
OV1_PDEN
V1_HSYNC
V1_VSYNC
V1_VDCLK_I
OV1 _H
OV1_V
OV1_VCLK
SDRAM BUS
D:128,A:11,BA:2,Ctrl:13
SDCLK=100MHz
DO_RA[9..2]
DO_GA[9..2]
DO_BA[9..2]
DO_HSYNC
DO_VSYNC
DO_HDISP
DCLK
MCK_REF
8
8
8
LCLK
D[23..16]
D[15..8]
D[7..0]
HSYNC
VSYNC
DE
IDCK+
E
DGE
RST
TX
MDA
MCK
PT
B3
PTA1
MON_DET
-RST
_PL
PTC5
HVSEL
PTA0
PTD7
PTE6
SEL _CD
SAD C_OE
CAR D_RST
P XOE
THER MO
B SREQ
CKIO(24MHz)
IRQ4
IRQ3
PTB7
PTC7
AN7
PTE6
CKIO
IRQ0
BINT
CS2
WAIT
PTD2
PTD5
BCLK
XBCS
BWAIT
XRESET
PLL_S
BD,BA
CPU BUS D:16,A:26
D[15..0],A[25..0]
SCK1
SCK2
EXTAL
XT
AL
RESE
TP
CN3
DVI
RS232C
Driver&
Reciever
IC405
uPD4721G
TXD2
RXD2
CTS2
RTS2
CN
7
FPC 50pin (TO MAIN PWB)
I2C=CH1,2,3, SERIAL=CH1
IRQ1
4
SSYSTEM
P C_V
10
IO_STB
CN
1
15pin
SERIAL=CH0
PT
B6
PTE7
FLASH_W
SRST
4
5
23
1
CSEN1
2
CSEN2
14
12
35
9
SENCE
SMPOW
7
AN
2
6
CCKM
S1
15
FWMODEN
PT
D1
PT
F0
FLAS HWP
PTE1
FST
ATUS
FLWP
FLASH
2Mx16bit
IC27
LH28F320S3NS
-C S0
DRAM 1Mx16bit
IC28
MSM51V18165D
PT
D6
16
HOTPLUG
ACL_S IG
ACL_S IG
44
5
PTG2
KOUTEI
12
CLR_ SW
CLR_ SW
PTD4
DAC_DATA
PTJ4
13
16
PTJ5
DAC_CLK
8
PTE3
ACL_SW
25
PTE2
RES_OUT3
PTE1
3
S RESET
PTG1
15
AW_ DATA
PTC4
1
TV_COL2
PTC0
2
TV_COL1
PTB2
26
HPMUTE
1
PTB0
24
LMUTE
PTJ7
14
SH_ON
PTA5
18
AWC S_R
PTA3
17
AWC S_W
48
AN0
AG C1
AN1
47
AG C2
50
49
AN4
AN3
AF T1
AF T2
20
19
AN6
AN5
PSE L1
PSE L2
6
WP
STS
VPP
A20
A20
CN
9
1:VD+5
3:VA+5
5,6:VD+2.5
8:VD+3.3
10:V-5
12:VA+12
13:VD+5BK
X1
MH
TXD1
RXD1
TXD0
RXD0
RXD 1_T
TXD 1_T
RXD0_M
TXD0_M
RXD 1_T
TXD 1_T
8
9
42
41
RXD 1_T
TXD 1_T
R1077
R1078
R1105
R1106
PTC6
X6
25.175MHz
VGA_OE
WXGA_OE
VGA_ OE
WXGA_OE
CE
2A
CK
E
FPC 30pin  TO MAIN PWB
CXA3506R
VCO 
WHISKER
CORRECTIO
N CIRCUIT
IC423, IC424
VIDEO SIGNAL
PEAK DETECTION
V1 ADC
RT, RB SETTING 
CIRCUIT
IC319-322
HY57V653220BTC-7  4 PCS.
RESET CIRCUIT
+2.5V IC19 PST623XW
+3.3V IC2 PST600IW
I
2
C=CH1
(TO MONITOR)
13pin (TO MAIN PWB)
POWER CONNECTOR
CN5
RS232C
SERIAL=CH2
INTERNAL 72MHz
EXTERNAL 24MHz
SERIAL CONNECTION FOR 
CE01 ONLY
(R1081, R1080)
CVIC INTERNAL SUPPLY VOLTAGE 
SELECTOR
R1077 MOUNTED: VD+2.5V=2.5V
R1078 MOUNTED: VD+2.5V=1.8V
CVIC INTERNAL SUPPLY VOLTAGE 
MONITOR
R1105 MOUNTED: VD+2.5V=2.5V
R1106 MOUNTED: VD+2.5V=1.8V
PC 
DDC
DETECT
FLASH WRITE AT FWMODEN=LOW
61
60
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
PZ-43MR2E
PZ-50MR2E
PC I/F BLOCK DIAGRAM
V0
A/D
Amp
PLL
IC4
CXA3506R
I
2
C=CH2
5V->3.3V
Reg
IC8 PQ2 0VZ11
X5
79.794MHz
DO_VS YNC
DO_HS YNC
LCLK(79.79 4MHz)
X4
25MHz
EEPROM
IC3
AT24C1 28N
I
2
C=CH3
CVIC
IC25
V1
A/D
IC310
TLC57 33A
12V->5VReg
IC7 PQ0 5TZ11
TMDS(4ch)
PanelLink
HDCP
Transmitter
IC413
SiI168
I
2
C=CH1
CPU
IC1
SH7709
I
2
C
 PORT
CH1 Do:PTB4,Di:PTG5,Clk:PT B5
CH2 Do:PTC1,Di:PTF2,Clk:PTC2
CH3 Do:PTA6,Di:PTG6,Clk:PTA7
CH4 Do:PTD0,Di:PTG4,Clk:PTA4
PC_ C3
HV SEL
OV0 _H
V1
PLL
IC328
TLC 2933IPW
12V->9V R eg
IC415 B A09FP
OV0_CLP
5V->3.3V R eg
IC412 PQ1 R33
DO_HD ISP
EEPROM
IC414
M24C32
X3
1.8432MHz
-RESET_C1
-
RST_P LL
-C1_I NT
CPCI-00 56CE
XPWR_SV
-CS2
-WAIT _C1
V0
Sync
Sel
IC411
74LCX157
1B
2B
4B
1A
2A
4A
-A /+B
1Y
2Y
4Y
CN
8
7
9
10
PC _H
P C_V
P C_C
CN
6
18
17
29,3
0
MAIN _H
D
MAIN_VD
5
1
3
P C_R
RIN2
GIN2
BIN2
PC _G
P C_B
RIN1
GIN1
BIN1
25,2
6
21,2
2
MAI N_
B
MAI N_
G
MAI N_
R
ROUT
GOUT
BOUT
SYNCIN1
SYNCIN2
HOLD
CLPIN
DIVOUT
1/2C LK
XPOWERSAVE
RA[7..0]
RB[7..0]
GA[7..0]
GB[7..0]
BA[7..0]
BB[7. .0]
AIN
BIN
CIN
RT
RB
3.27V
1.17V
AO[8..1]
BO[8..1]
CO[8..1]
EXTCLP
CLK
- OE
FIN-A
FIN-B
PFDINH
VCOOUT
13,1
4
9,10
5,6
SUB _Y
SUB_ Cb
SUB_ Cr
SUB_
HD
2
1
SUB
_VD
About 60MHz
12pin  TO CONNECTOR PWB
SDRAM
512Kx128bitx4 BANK
8
V0_HSYNC
V0_VSYNC
V0_CSYNC
OV0_V
V0_HSYNR
OV0_HSYNR
V0_PDEN
OV0_PDEN
V0_CLP
OV0_CLP
V0_HSYNC2
V0_VDCLK_I
OV0_HSC2
OVCLK(Max60MHz)
V0_RA[7..0]
V0_RB[7..0]
V0_GA[7..0]
V0_GB[7..0]
V0_BA[7..0]
V0_BB[7..0]
8
8
8
8
8
XPW R_SV
V1_GA[7..0]
V1_BA[7..0]
V1_RA[7..0]
8
8
8
OV1_VCKO
(
15M Hz)
V1_VDCLK_O
OV1_CLP
V1_CLP
SAD C_OE
V1_HSYNR
V1_HSYNF
V1_PDEN
OV1_HSNR
OV1_HSNF
OV1_PDEN
V1_HSYNC
V1_VSYNC
V1_VDCLK_I
OV1 _H
OV1_V
OV1_VCLK
SDRAM BUS
D:128,A:11,BA:2,Ctrl:13
SDCLK=100MHz
DO_RA[9..2]
DO_GA[9..2]
DO_BA[9..2]
DO_HSYNC
DO_VSYNC
DO_HDISP
DCLK
MCK_REF
8
8
8
LCLK
D[23..16]
D[15..8]
D[7..0]
HSYNC
VSYNC
DE
IDCK+
E
DGE
RST
TX
MDA
MCK
PT
B3
PTA1
MON_DET
-RST
_PL
PTC5
HVSEL
PTA0
PTD7
PTE6
SEL _CD
SAD C_OE
CAR D_RST
P XOE
THER MO
B SREQ
CKIO(24MHz)
IRQ4
IRQ3
PTB7
PTC7
AN7
PTE6
CKIO
IRQ0
BINT
CS2
WAIT
PTD2
PTD5
BCLK
XBCS
BWAIT
XRESET
PLL_S
BD,BA
CPU BUS D:16,A:26
D[15..0],A[25..0]
SCK1
SCK2
EXTAL
XT
AL
RESE
TP
CN3
DVI
RS232C
Driver&
Reciever
IC405
uPD4721G
TXD2
RXD2
CTS2
RTS2
CN
7
FPC 50pin (TO MAIN PWB)
I2C=CH1,2,3, SERIAL=CH1
IRQ1
4
SSYSTEM
P C_V
10
IO_STB
CN
1
15pin
SERIAL=CH0
PT
B6
PTE7
FLASH_W
SRST
4
5
23
1
CSEN1
2
CSEN2
14
12
35
9
SENCE
SMPOW
7
AN
2
6
CCKM
S1
15
FWMODEN
PT
D1
PT
F0
FLAS HWP
PTE1
FST
ATUS
FLWP
FLASH
2Mx16bit
IC27
LH28F320S3NS
-C S0
DRAM 1Mx16bit
IC28
MSM51V18165D
PT
D6
16
HOTPLUG
ACL_S IG
ACL_S IG
44
5
PTG2
KOUTEI
12
CLR_ SW
CLR_ SW
PTD4
DAC_DATA
PTJ4
13
16
PTJ5
DAC_CLK
8
PTE3
ACL_SW
25
PTE2
RES_OUT3
PTE1
3
S RESET
PTG1
15
AW_ DATA
PTC4
1
TV_COL2
PTC0
2
TV_COL1
PTB2
26
HPMUTE
1
PTB0
24
LMUTE
PTJ7
14
SH_ON
PTA5
18
AWC S_R
PTA3
17
AWC S_W
48
AN0
AG C1
AN1
47
AG C2
50
49
AN4
AN3
AF T1
AF T2
20
19
AN6
AN5
PSE L1
PSE L2
6
WP
STS
VPP
A20
A20
CN
9
1:VD+5
3:VA+5
5,6:VD+2.5
8:VD+3.3
10:V-5
12:VA+12
13:VD+5BK
X1
MH
TXD1
RXD1
TXD0
RXD0
RXD 1_T
TXD 1_T
RXD0_M
TXD0_M
RXD 1_T
TXD 1_T
8
9
42
41
RXD 1_T
TXD 1_T
R1077
R1078
R1105
R1106
PTC6
X6
25.175MHz
VGA_OE
WXGA_OE
VGA_ OE
WXGA_OE
CE
2A
CK
E
FPC 30pin  TO MAIN PWB
CXA3506R
VCO 
WHISKER
CORRECTIO
N CIRCUIT
IC423, IC424
VIDEO SIGNAL
PEAK DETECTION
V1 ADC
RT, RB SETTING 
CIRCUIT
IC319-322
HY57V653220BTC-7  4 PCS.
RESET CIRCUIT
+2.5V IC19 PST623XW
+3.3V IC2 PST600IW
I
2
C=CH1
(TO MONITOR)
13pin (TO MAIN PWB)
POWER CONNECTOR
CN5
RS232C
SERIAL=CH2
INTERNAL 72MHz
EXTERNAL 24MHz
SERIAL CONNECTION FOR 
CE01 ONLY
(R1081, R1080)
CVIC INTERNAL SUPPLY VOLTAGE 
SELECTOR
R1077 MOUNTED: VD+2.5V=2.5V
R1078 MOUNTED: VD+2.5V=1.8V
CVIC INTERNAL SUPPLY VOLTAGE 
MONITOR
R1105 MOUNTED: VD+2.5V=2.5V
R1106 MOUNTED: VD+2.5V=1.8V
PC 
DDC
DETECT
FLASH WRITE AT FWMODEN=LOW
61
60
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
PZ-43MR2E
PZ-50MR2E
PC I/F BLOCK DIAGRAM
V0
A/D
Amp
PLL
IC4
CXA3506R
I
2
C=CH2
5V->3.3V
Reg
IC8 PQ2 0VZ11
X5
79.794MHz
DO_VS YNC
DO_HS YNC
LCLK(79.79 4MHz)
X4
25MHz
EEPROM
IC3
AT24C1 28N
I
2
C=CH3
CVIC
IC25
V1
A/D
IC310
TLC57 33A
12V->5VReg
IC7 PQ0 5TZ11
TMDS(4ch)
PanelLink
HDCP
Transmitter
IC413
SiI168
I
2
C=CH1
CPU
IC1
SH7709
I
2
C
 PORT
CH1 Do:PTB4,Di:PTG5,Clk:PT B5
CH2 Do:PTC1,Di:PTF2,Clk:PTC2
CH3 Do:PTA6,Di:PTG6,Clk:PTA7
CH4 Do:PTD0,Di:PTG4,Clk:PTA4
PC_ C3
HV SEL
OV0 _H
V1
PLL
IC328
TLC 2933IPW
12V->9V R eg
IC415 B A09FP
OV0_CLP
5V->3.3V R eg
IC412 PQ1 R33
DO_HD ISP
EEPROM
IC414
M24C32
X3
1.8432MHz
-RESET_C1
-
RST_P LL
-C1_I NT
CPCI-00 56CE
XPWR_SV
-CS2
-WAIT _C1
V0
Sync
Sel
IC411
74LCX157
1B
2B
4B
1A
2A
4A
-A /+B
1Y
2Y
4Y
CN
8
7
9
10
PC _H
P C_V
P C_C
CN
6
18
17
29,3
0
MAIN _H
D
MAIN_VD
5
1
3
P C_R
RIN2
GIN2
BIN2
PC _G
P C_B
RIN1
GIN1
BIN1
25,2
6
21,2
2
MAI N_
B
MAI N_
G
MAI N_
R
ROUT
GOUT
BOUT
SYNCIN1
SYNCIN2
HOLD
CLPIN
DIVOUT
1/2C LK
XPOWERSAVE
RA[7..0]
RB[7..0]
GA[7..0]
GB[7..0]
BA[7..0]
BB[7. .0]
AIN
BIN
CIN
RT
RB
3.27V
1.17V
AO[8..1]
BO[8..1]
CO[8..1]
EXTCLP
CLK
- OE
FIN-A
FIN-B
PFDINH
VCOOUT
13,1
4
9,10
5,6
SUB _Y
SUB_ Cb
SUB_ Cr
SUB_
HD
2
1
SUB
_VD
About 60MHz
12pin  TO CONNECTOR PWB
SDRAM
512Kx128bitx4 BANK
8
V0_HSYNC
V0_VSYNC
V0_CSYNC
OV0_V
V0_HSYNR
OV0_HSYNR
V0_PDEN
OV0_PDEN
V0_CLP
OV0_CLP
V0_HSYNC2
V0_VDCLK_I
OV0_HSC2
OVCLK(Max60MHz)
V0_RA[7..0]
V0_RB[7..0]
V0_GA[7..0]
V0_GB[7..0]
V0_BA[7..0]
V0_BB[7..0]
8
8
8
8
8
XPW R_SV
V1_GA[7..0]
V1_BA[7..0]
V1_RA[7..0]
8
8
8
OV1_VCKO
(
15M Hz)
V1_VDCLK_O
OV1_CLP
V1_CLP
SAD C_OE
V1_HSYNR
V1_HSYNF
V1_PDEN
OV1_HSNR
OV1_HSNF
OV1_PDEN
V1_HSYNC
V1_VSYNC
V1_VDCLK_I
OV1 _H
OV1_V
OV1_VCLK
SDRAM BUS
D:128,A:11,BA:2,Ctrl:13
SDCLK=100MHz
DO_RA[9..2]
DO_GA[9..2]
DO_BA[9..2]
DO_HSYNC
DO_VSYNC
DO_HDISP
DCLK
MCK_REF
8
8
8
LCLK
D[23..16]
D[15..8]
D[7..0]
HSYNC
VSYNC
DE
IDCK+
E
DGE
RST
TX
MDA
MCK
PT
B3
PTA1
MON_DET
-RST
_PL
PTC5
HVSEL
PTA0
PTD7
PTE6
SEL _CD
SAD C_OE
CAR D_RST
P XOE
THER MO
B SREQ
CKIO(24MHz)
IRQ4
IRQ3
PTB7
PTC7
AN7
PTE6
CKIO
IRQ0
BINT
CS2
WAIT
PTD2
PTD5
BCLK
XBCS
BWAIT
XRESET
PLL_S
BD,BA
CPU BUS D:16,A:26
D[15..0],A[25..0]
SCK1
SCK2
EXTAL
XT
AL
RESE
TP
CN3
DVI
RS232C
Driver&
Reciever
IC405
uPD4721G
TXD2
RXD2
CTS2
RTS2
CN
7
FPC 50pin (TO MAIN PWB)
I2C=CH1,2,3, SERIAL=CH1
IRQ1
4
SSYSTEM
P C_V
10
IO_STB
CN
1
15pin
SERIAL=CH0
PT
B6
PTE7
FLASH_W
SRST
4
5
23
1
CSEN1
2
CSEN2
14
12
35
9
SENCE
SMPOW
7
AN
2
6
CCKM
S1
15
FWMODEN
PT
D1
PT
F0
FLAS HWP
PTE1
FST
ATUS
FLWP
FLASH
2Mx16bit
IC27
LH28F320S3NS
-C S0
DRAM 1Mx16bit
IC28
MSM51V18165D
PT
D6
16
HOTPLUG
ACL_S IG
ACL_S IG
44
5
PTG2
KOUTEI
12
CLR_ SW
CLR_ SW
PTD4
DAC_DATA
PTJ4
13
16
PTJ5
DAC_CLK
8
PTE3
ACL_SW
25
PTE2
RES_OUT3
PTE1
3
S RESET
PTG1
15
AW_ DATA
PTC4
1
TV_COL2
PTC0
2
TV_COL1
PTB2
26
HPMUTE
1
PTB0
24
LMUTE
PTJ7
14
SH_ON
PTA5
18
AWC S_R
PTA3
17
AWC S_W
48
AN0
AG C1
AN1
47
AG C2
50
49
AN4
AN3
AF T1
AF T2
20
19
AN6
AN5
PSE L1
PSE L2
6
WP
STS
VPP
A20
A20
CN
9
1:VD+5
3:VA+5
5,6:VD+2.5
8:VD+3.3
10:V-5
12:VA+12
13:VD+5BK
X1
MH
TXD1
RXD1
TXD0
RXD0
RXD 1_T
TXD 1_T
RXD0_M
TXD0_M
RXD 1_T
TXD 1_T
8
9
42
41
RXD 1_T
TXD 1_T
R1077
R1078
R1105
R1106
PTC6
X6
25.175MHz
VGA_OE
WXGA_OE
VGA_ OE
WXGA_OE
CE
2A
CK
E
FPC 30pin  TO MAIN PWB
CXA3506R
VCO 
WHISKER
CORRECTIO
N CIRCUIT
IC423, IC424
VIDEO SIGNAL
PEAK DETECTION
V1 ADC
RT, RB SETTING 
CIRCUIT
IC319-322
HY57V653220BTC-7  4 PCS.
RESET CIRCUIT
+2.5V IC19 PST623XW
+3.3V IC2 PST600IW
I
2
C=CH1
(TO MONITOR)
13pin (TO MAIN PWB)
POWER CONNECTOR
CN5
RS232C
SERIAL=CH2
INTERNAL 72MHz
EXTERNAL 24MHz
SERIAL CONNECTION FOR 
CE01 ONLY
(R1081, R1080)
CVIC INTERNAL SUPPLY VOLTAGE 
SELECTOR
R1077 MOUNTED: VD+2.5V=2.5V
R1078 MOUNTED: VD+2.5V=1.8V
CVIC INTERNAL SUPPLY VOLTAGE 
MONITOR
R1105 MOUNTED: VD+2.5V=2.5V
R1106 MOUNTED: VD+2.5V=1.8V
PC 
DDC
DETECT
FLASH WRITE AT FWMODEN=LOW
Page of 7
Display

Sharp PZ-50MR2E (serv.man10) Service Manual ▷ Download