DOWNLOAD Sharp PZ-43MR2E (serv.man8) Service Manual ↓ Size: 531.78 KB | Pages: 23 in PDF or view online for FREE

Model
PZ-43MR2E (serv.man8)
Pages
23
Size
531.78 KB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD / Description of major functions
File
pz-43mr2e-sm8.pdf
Date

Sharp PZ-43MR2E (serv.man8) Service Manual ▷ View online

27
PZ-43MR2E
PZ-50MR2E
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Pin Function
Pin No.
Pin Name
I/O
Pin Function
P3.0-P3.7
P4.2-P4.3(P4.7)
XROM
ENE
STOP
OCF
EXTIF
CVBS
HS/SC
VS/P4.7
RST
XTAL2
XTAL1
R
G
B
BLANK/COR
WR
RD
FL_PGM
FL_RST
ALE
PSEN
FL_CE
VDD2.5
VDDA2.5
VDD3.3
VSS
VSSA
I/O
I/O
I
I
I
O
I
I
I/O
I
O
I
O
O
O
O
O
O
I
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O
O
I






Port 3 is an 8-bit bi-directional I/O port with internal pull-up resistors, Port 3 pins that
have 1 written to them are pulled high by the internal pull-up resistors and in that state
can be used as inputs,
To use the secondary functions of Port 3, the corresponding output latch must be
programmed to a one (1) for that function to operate. The secondary functions are as
follows:
»
 Alternate function
P3.0 : ODD/EVEN indicate output
P3.1 : external extra interrupt 0 (INTX0)/UART(TXD)
P3.2 : interrupt 0 input/timer 0 gate control input)INT0)
P3.3 : interrupt 1 input/timer 1 gate control input)INT1)
P3.4 : counter 0 input (T0)
P3.5 : counter 1 input (T1) or In master mode HS or VCS output.
P3.7 : external extra interrupt 0 (INTX1)/UART (RXD)
Port 4 is a bi-directional I/O port with internal pull-up resistors.
Port 4 pins that have 1 written to them are pulled high by the internal pull-up resistors
and in that state can be used as inputs.
Secondary functions
P4.2: RD, Read line. This signal is same as the to output of the pin RD available in
some packages.
P4.3: WR write line. This signal is same as the output of the pin WE, which is only
available in some package.
This pin must be pulled low to access external ROM.
Enable Emulation
Only if this pin set to zero externally, STOP and OCF are operational. ENE has an
internal pull-up resistor which switches automatically to non-emulation mode if ENE is
not connected.
STOP
Emulation control line; Driving a low level during the input phase freezes the real time
relevant internal peripherals such as timers and interrupt controller.
Opcode Fetch
Emulation control line; A high level driven by the controller during output phase
indicates the beginning of a new instruction.
CVBS input for the acquisition circuit.
In slave mode Horizontal sync input or sandcastle input for display synchronization .In
master mode HS or VCS output.
Vertical sync input/output for display synchronization.
Can also be used as digital input P4.7.
Furthermore this pin can be selected as an ODD/EVEN indicator alternatively to P3.0.
A low level on this pin resets the device. An internal pull-up resistor permits power-on
reset using only one external capacitor connected to Vss.
Output of the inverting oscillator amplifier.
Input of the inverting oscillator amplifier.
Red
Green
Blue
Contrast reduction and blanking.
Control output; indicates a write access to the internal XRAM; can be used as a write
strobe for writing data into an external data RAM by a MOVX instruction.
This signal is also available as P4.3.
Control output; indicates a read access to the internal XRAM; can be used for latching
data from the data bus into an external data RAM by a MOVX instruction.
This signal is also available as P4.2.
All the pins prefix by Flax are test pins which must be left open.
All the pins prefix by Flax are test pins which must be left open.
Address Latch Enable.
Program Store Enable
is a control output signal which is usually connected to OE input line of the external
program memory to enable the data output.
All the pins prefix by Flax are test pins which must be left open.
Supply voltage (2.5V).
Supply voltage for analog components (2.5V).
Input/output (3.3V).
Ground (0V).
Ground for analog components.
28
PZ-43MR2E
PZ-50MR2E
Ë
RH-iX3371CEZZ (ASSY: IC2501)
»
Multi Standard Sound Processor
»
Block Diagram
29
PZ-43MR2E
PZ-50MR2E
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»
Pin Function
Pin No.
Pin Name
I/O
Pin Function
NC
I2C_CL
I2C_DA
I2S_CL
I2S_WS
I2S_DA_OUT
I2S_DA_IN1
ADR_DA
ADR_WS
ADR_CL
DVSUP
DVSS
I2S_DA_IN2
NC
RESETQ
NC
DACA_R
DACA_L
VREF2
DACM_R
DACM_L
NC
DACM_SUB
NC
SC2_OUT_R
SC2_OUT_L
VREF1
SC1_OUT_R
SC1_OUT_L
CAPL_A
AHVSUP
CAPL_M
NC
AHVSS
AGNDC
NC
SC4_IN_L
SC4_IN_R
ASG4
SC3_IN_L
SC3_IN_R
ASG2
SC2_IN_L
SC2_IN_R
ASG1
SC1_IN_L
SC1_IN_R
VREFTOP
NC
MONO_IN
AVSS
NC
AVSUP
ANA_IN1+
ANA_IN-
ANA_IN2+
TESTEN
XTAL_IN
XTAL_OUT
TP
AUD_CL_OUT
NC
D_CTR_I/O_1
D_CTR_I/O_0
ADR_SEL
STANDBYQ
I/O
I/O
I/O
I/O
O
I
O
O
O

I
I
O
O
O
O
O
O
O
O
O






I
I
I
I
I
I
I
I

I


I
I
I
I
I
O
O
I/O
I/O
I
I
Not connected
I2C clock
I2C data
I2S clock
I2S word strobe
I2S data output
I2S1 data input
ADR data output
ADR word strobe
ADR clock
Digital power supply 5V
Digital ground
I2S2-data input
Not connected
Power-on-reset
Not connected
Headphone out, right
Headphone out, left
Reference ground 2
Loudspeaker out, right
Loudspeaker out, left
Not connected
Subwoofer output
Not connected
SCART 2 output, right
SCART 2 output, left
Reference ground 1
SCART 1 output, right
SCART 1 output, left
Volume capacitor AUX
Analog power supply 8V
Volume capacitor MAIN
Not connected
Analog ground
Analog reference voltage
Not connected
SCART 4 input, left
SCART 4 input, right
Analog Shield Ground 4
SCART 3 input, left
SCART 3 input, right
Analog Shield Ground 2
SCART 2 input, left
SCART 2 input, right
Analog Shield Ground 1
SCART 1 input, left
SCART 1 input, right
Reference voltage IF A/D converter
Not connected
Mono input
Analog ground
Not connected
Analog power supply 5V
IF input 1
IF common(can be left vacant, only if IF input 1 is also not in use)
IF input 2(can be left vacant, only if IF input 1 is also not in use)
Test pin
Crystal oscillator
Test pin
Audio clock output (18.432MHz)
Not connected
D_CTR_I/O_1
D_CTR_I/O_0
I2C Bus address select
Stand-by (low-active)
30
PZ-43MR2E
PZ-50MR2E
Ë
VHiTB1274AF-1Q (ASSY: IC801, IC802)
»
VIDEO/CHROMA Processor
»
Block Diagram
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