DOWNLOAD Sharp PZ-43MR2E (serv.man8) Service Manual ↓ Size: 531.78 KB | Pages: 23 in PDF or view online for FREE

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35, 37, 41, 43, 47,
49, 54, 56, 60, 62
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VIDEO 1-L1
VIDEO 1-L2
VIDEO 1-L3
VIDEO 2-L1
VIDEO 2-L2
VIDEO 2-L3
VIDEO 3-L1
VIDEO 3-L2
VIDEO 3-L3
VCC

AVCC
VIDEO 2-Y
VIDEO 3-Y
TUNER-Y
VIDEO 1-Y
DGND
GND

VIDEO 2-Pb
VIDEO 2-Pr
VIDEO 3-Pb
VIDEO 3-Pr
TUNER-Pb
TUNER-Pr
VIDEO 1-Pb
VIDEO 1-Pr
VIDEO 2-SW
VIDEO 3-SW
MONO-SW
VIDEO 1-SW
ADDRESS
SDA
SCL
DVCC
L3 OUT
L2 OUT
L1 OUT
Pr OUT 3
Pb OUT 3
Y OUT 3
Pr OUT 2
Pb OUT 2
Y OUT 2
Pr OUT 1
Pb OUT 1
Y OUT 1

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I/O

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O
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Line input of D-terminal

Analog power supply (9V)

Y-signal input

GND

Pb, Pr signal input

Switch line of D-terminal

Slave address select pin
Data input of I2C bus
Clock input of I2C bus
Digital power supply (5V)
Line output for monitor

Video signal output

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99, 1, 3, 4, 2, 100,
98, 96
97, 94, 93, 89, 86,
84, 82, 79, 81, 83,
90, 85, 77, 78, 76,
71, 69
70, 68, 67

9, 10, 11, 12, 13,
14, 15, 16
41, 42, 43, 44, 45,
46, 47, 62

24, 25, 26, 27

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D0-D7

A0-A16

A17-A19/
P4.0, P4.1, P4.4

P0.0-P0.7

P1.0-P1.7
(PWM)

P2.0-P2.3
(ADC)

I/O

O

I/O

I/O

I/O

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Data bus for external memory or data RAM.

Address bus for external program memory or data RAM.

After power-on P4.0,P4.1,P4.4 work as additional address lines A17…A19.
In port mode, these port lines act as bi-directional I/O port with internal pull-up
resistors. Port pins that have ‘1’ written to them are pulled high by the internal pull-up
resistors and in that state can be used as inputs.
Port 0 is a 8-bit open drain bi-directional I/O-port. Port 0 pins that have 1 written to
them float: in this state they can be used as high impedance inputs.
Port is a 8-bit bi-directional multifunction I/O port with internal pull-up resistors. Port 1
pins that have 1 written to them are pulled high by the internal pull-up resistors and in
that state can be used as inputs.
The secondary functions of port 1 pins are:
Port bits P1.0-P1.5 contain the 6 output channels of the 8-bit pulse width modulation
unit.
Port bits P1.6-P1.7 contain the two output channels of the 14-bit pulse width
modulation unit.
Port 2 is a 4-bit input port without pull-up resistors.
Port 2 also works as analog input for the 4-channel-ADC.

31, 32, 33, 34, 35,
36, 37, 38

48, 49

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22, 56
8, 40, 75, 92
7, 39, 74, 91,
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28, 51, 54, 61, 63,
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P3.0-P3.7

P4.2-P4.3(P4.7)

XROM
ENE

STOP

OCF

EXTIF
CVBS
HS/SC

VS/P4.7

RST

XTAL2
XTAL1
R
G
B
BLANK/COR
WR

RD

FL_PGM
FL_RST
ALE
PSEN

FL_CE
VDD2.5
VDDA2.5
VDD3.3
VSS
VSSA
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I/O

I/O

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Port 3 is an 8-bit bi-directional I/O port with internal pull-up resistors, Port 3 pins that
have 1 written to them are pulled high by the internal pull-up resistors and in that state
can be used as inputs,
To use the secondary functions of Port 3, the corresponding output latch must be
programmed to a one (1) for that function to operate. The secondary functions are as
follows:

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 Alternate function

P3.0 : ODD/EVEN indicate output
P3.1 : external extra interrupt 0 (INTX0)/UART(TXD)
P3.2 : interrupt 0 input/timer 0 gate control input)INT0)
P3.3 : interrupt 1 input/timer 1 gate control input)INT1)
P3.4 : counter 0 input (T0)
P3.5 : counter 1 input (T1) or In master mode HS or VCS output.
P3.7 : external extra interrupt 0 (INTX1)/UART (RXD)
Port 4 is a bi-directional I/O port with internal pull-up resistors.
Port 4 pins that have 1 written to them are pulled high by the internal pull-up resistors
and in that state can be used as inputs.
Secondary functions
P4.2: RD, Read line. This signal is same as the to output of the pin RD available in
some packages.
P4.3: WR write line. This signal is same as the output of the pin WE, which is only
available in some package.
This pin must be pulled low to access external ROM.
Enable Emulation
Only if this pin set to zero externally, STOP and OCF are operational. ENE has an
internal pull-up resistor which switches automatically to non-emulation mode if ENE is
not connected.
STOP
Emulation control line; Driving a low level during the input phase freezes the real time
relevant internal peripherals such as timers and interrupt controller.
Opcode Fetch
Emulation control line; A high level driven by the controller during output phase
indicates the beginning of a new instruction.

CVBS input for the acquisition circuit.
In slave mode Horizontal sync input or sandcastle input for display synchronization .In
master mode HS or VCS output.
Vertical sync input/output for display synchronization.
Can also be used as digital input P4.7.
Furthermore this pin can be selected as an ODD/EVEN indicator alternatively to P3.0.
A low level on this pin resets the device. An internal pull-up resistor permits power-on
reset using only one external capacitor connected to Vss.
Output of the inverting oscillator amplifier.
Input of the inverting oscillator amplifier.
Red
Green
Blue
Contrast reduction and blanking.
Control output; indicates a write access to the internal XRAM; can be used as a write
strobe for writing data into an external data RAM by a MOVX instruction.
This signal is also available as P4.3.
Control output; indicates a read access to the internal XRAM; can be used for latching
data from the data bus into an external data RAM by a MOVX instruction.
This signal is also available as P4.2.
All the pins prefix by Flax are test pins which must be left open.
All the pins prefix by Flax are test pins which must be left open.
Address Latch Enable.
Program Store Enable
is a control output signal which is usually connected to OE input line of the external
program memory to enable the data output.
All the pins prefix by Flax are test pins which must be left open.
Supply voltage (2.5V).
Supply voltage for analog components (2.5V).
Input/output (3.3V).
Ground (0V).
Ground for analog components.

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