DOWNLOAD Sharp PZ-43MR2E (serv.man8) Service Manual ↓ Size: 531.78 KB | Pages: 23 in PDF or view online for FREE

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HD1-IN
HD2-IN
HD3-IN
VD1-IN
VD2-IN
VD3-IN
ANALOG GND
AFC FILTER

HVCO
VCC
DAC1
(V. SYNC output)
DAC2
(H/C. SYNC output)
DAC3

CP-OUT
HD1-OUT
HD2-OUT

DIGITAL GND
SDA
SCL
ADDRESS SW
SYNC1-IN
SYNC2-IN
VD1-OUT
VD2-OUT

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I/O

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Input the horizontal synchronizing signal.
It’s polarity corresponds to both positive and negative.
Input from this pin does not be synchronized internally.
Input the horizontal vertical signal.
It’s polarity corresponds to both positive and negative.
Input from this pin does not be synchronized internally.
The GND pin for analog circuit block.
Connect the filter for horizontal AFC. The  frequency of the horizontal output is varied
by the volyage at this pin.
Connect the ceramic oscillator for horizontal oscillator.
The VCC pin. (9.0V)
DAC1 output pin. When TEST mode, VD or vertical sync signal to frequency counter
circuit is output.
DAC2 output pin. When TEST mode, HD or composite sync signal to frequency
counter circuit is output.
DAC3 output pin. This pin is open-collector system. When TEST mode, test pilses for
the shipping is output.
Clamp pulse output pin. CP mode at synchronization circuit is output.
HD output pin. This pin is open-collector system.
HD1/HD2 does not be synchronizing and they are output from this pin.
It’s polarity is switched by BUS write function.
The GND pin for logic circuit block.
The SDA pin for I2C BUS.
The SCL pin for I2C BUS.
Slave address switch.
Input a signal to separate sync signal.

VD output pin. This pin is open-collector system.
VD1/VD2 does not be synchronizing and they are output from this pin.
It’s polarity is switched by BUS write function.

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CLPO

ADIN
RB
ADVS
ADVD
RT
ACO

DAVD
AYO

DAVS
VG
VRF
IRF
VB
TEST
DVDD
DVSS
MOD2
MOD1

VEH3
VEH2
VEH1
PNR
DTR
NTPL2

NTPL1

APCN
TRAP
FIN
CKSL
PLSL
MCKO
ADCK
CPO
PLVS
VCV
PLVD
CLVD
CLPEN
CLVS

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Built-in clamp circuit current output terminal. To be connected to ADIN when built-in
clamp is used.
Comb filter analog input (A/D converter) terminal.
A/D converter reference bottom voltage. (standard 0.52V)
A/D converter analog grounding terminal.
A/D converter analog power terminal. (5.0V)
A/D converter reference top voltage. (standard 2.6V)
Analog chroma signal output terminal. Resistance to be added between this pin and
GND for obtaining the output.
D/A converter analog power terminal. (5.0V)
Analog luminance signal output terminal. Resistance to be added between this pin and
GND for obtaining the output.
D/A converter analog grounding terminal.
D/A converter terminal.
Y,C ch D/A converter output full-scale setting terminal.
x16 resistance to be connected against D/A converter output resistance “R”.
D/A converter terminal.
Test terminal. (fixed at Low)
Digital power terminal. (5.0V)
Digital grounding terminal.
Y/C separation mode setting terminal.

MODE2

MOD1

L

L

Most suitable process mode

H

L

BPF separation mode

Vertical contour enhancement setting terminal.

L: NTSC  H: PAL, M-PAL, N-PAL
Fixed at Low.
NTSC/PAL/M-PAL/N-PAL mode setting terminal.

NTPL2

NTPL1

L

L

NTSC

H

H

PAL

H

L

M-PAL

H

H

N-PAL

Horizontal aperture correction circuit setting terminal. L: off, H: on
Trap filter circuit setting terminal. L: off, H: on
Clock input terminal.
PLL control terminal. VCO oscillator output’s 4fsc clock to be fed in.
FIN input fsc to be selected.
Clock (4fsc) output terminal.
A/D converter clock input terminal. To be connected to MCKO.
PLL phase comparator output terminal.
PLL analog grounding terminal.
VCO control voltage input terminal.
PLL analog power terminal. (5.0V)
Clamp D/A converter analog power terminal. (5.0V)
Clamp circuit enable terminal.
Clamp D/A converter analog grounding terminal.