Sharp PZ-43MR2E (serv.man8) Service Manual ▷ View online
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PZ-43MR2E
PZ-50MR2E
PZ-50MR2E
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IC405/IC402 (CXD2064Q)
This IC is a comb filter in the applicable field for both the NTSC and PAL systems. It performs the Y/C separation
of the main and sub channel video signals that have been output from IC1801.
This IC is a comb filter in the applicable field for both the NTSC and PAL systems. It performs the Y/C separation
of the main and sub channel video signals that have been output from IC1801.
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IC407/IC404 (ML6428C1)
This IC is a 6.7 MHz low-pass filter.
This IC is a 6.7 MHz low-pass filter.
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IC810/IC804 (IX3473CE)
This IC is a 6.7 MHz low-pass filter incorporating a 6 dB amplifier.
This IC is a 6.7 MHz low-pass filter incorporating a 6 dB amplifier.
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IC811 (IX3474CE)
This IC is a 30 MHz low-pass filter incorporating a 6 dB amplifier.
This IC is a 30 MHz low-pass filter incorporating a 6 dB amplifier.
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IC1702 (FA3675CE)
This IC is designed to control the 6-channel PWM switching regulator.
With 5 step-up switching regulator lines incorporated, the IC converts +10V to +2.5V, +3.3V and +5.8V.
Also with a step-down switching regulator line incorporated, the IC converts +10V to +6.0V, -5.0V, +12V and +35V.
The lines are individually turned on and off.
This IC is designed to control the 6-channel PWM switching regulator.
With 5 step-up switching regulator lines incorporated, the IC converts +10V to +2.5V, +3.3V and +5.8V.
Also with a step-down switching regulator line incorporated, the IC converts +10V to +6.0V, -5.0V, +12V and +35V.
The lines are individually turned on and off.
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Description of Functions of Main ICs on PC I/F Unit
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IC4 (CXA3506R)
This IC is an A/D converter that incorporates a 3-channel, 8-bit, 120 MSPS amplifier and PLL. It is used for the
video signals input to the PC I/F unit on the main channel in the 1-screen and 2-screen modes, and also for the
video signals input from the front for the PC.
The video signals (analog RGB) from the CN6 are input to IN1 of IC4.
For the PC, the video signals (analog RGB) from CN8 are input to IN2 of IC4.
The input video signals are converted into digital signals and then sent to IC25.
This IC is an A/D converter that incorporates a 3-channel, 8-bit, 120 MSPS amplifier and PLL. It is used for the
video signals input to the PC I/F unit on the main channel in the 1-screen and 2-screen modes, and also for the
video signals input from the front for the PC.
The video signals (analog RGB) from the CN6 are input to IN1 of IC4.
For the PC, the video signals (analog RGB) from CN8 are input to IN2 of IC4.
The input video signals are converted into digital signals and then sent to IC25.
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IC310 (TLC5733A)
This IC is a 3-channel, 8-bit, 20 MSPS A/D converter.
It is used for the sub-channel of the video signals input to the PC I/F Unit in the 2-screen mode.
The video signals (analog Y, Cb, Cr) from CN6 are input to IC310.
The video signals input to this IC are converted into digital signals and then sent to IC25.
This IC is a 3-channel, 8-bit, 20 MSPS A/D converter.
It is used for the sub-channel of the video signals input to the PC I/F Unit in the 2-screen mode.
The video signals (analog Y, Cb, Cr) from CN6 are input to IC310.
The video signals input to this IC are converted into digital signals and then sent to IC25.
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IC25 (IX3434CE)
This IC performs the I/P conversion and scaling to match the digitalized video with the output resolution, and also
the data conversion.
It has two input lines, V0 and V1. The V0 line is used to process the RGB, composite, and skirt signals input to the
480i and 580i components for the sub-channel in the 2-screen mode. The V1 line is used to process all the signals
as well as V1 for the main channel in the 1-screen and 2-screen modes.
The IC25 detects what resolution is input from the input synchronizing signal; creates H synchronization in
accordance with the frequency division ratio; creates the clamp signal in accordance with the input synchronizing
signal; and performs the data matrix conversion.
The video signals input to this IC is sent to IC413.
This IC performs the I/P conversion and scaling to match the digitalized video with the output resolution, and also
the data conversion.
It has two input lines, V0 and V1. The V0 line is used to process the RGB, composite, and skirt signals input to the
480i and 580i components for the sub-channel in the 2-screen mode. The V1 line is used to process all the signals
as well as V1 for the main channel in the 1-screen and 2-screen modes.
The IC25 detects what resolution is input from the input synchronizing signal; creates H synchronization in
accordance with the frequency division ratio; creates the clamp signal in accordance with the input synchronizing
signal; and performs the data matrix conversion.
The video signals input to this IC is sent to IC413.
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IC413 (SiI168)
This IC is a panel link transmitter.
It converts the 8-bit RGB video data output from IC25 into the differential TMDS signals and then digitally transmits
the converted signals to the monitor.
The TMDS signals are transmitted at the frequency 10 times higher than the clock frequency.
This IC is a panel link transmitter.
It converts the 8-bit RGB video data output from IC25 into the differential TMDS signals and then digitally transmits
the converted signals to the monitor.
The TMDS signals are transmitted at the frequency 10 times higher than the clock frequency.
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IC1 (IX3270CE)
This IC is a 1-chip RISC microprocessor.
It performs communication with the monitor and operates the system.
The IC1 also controls each IC in the AVC system and partially manages the power source.
This IC is a 1-chip RISC microprocessor.
It performs communication with the monitor and operates the system.
The IC1 also controls each IC in the AVC system and partially manages the power source.
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IC405 (uPD4721)
This IC is an RS-232 line driver receiver conforming to the EIA/TIA-232-E standard.
The IC405, when connected to a PC, allows for externally controlling the system.
It is also applicable for upgrading IC1.
This IC is an RS-232 line driver receiver conforming to the EIA/TIA-232-E standard.
The IC405, when connected to a PC, allows for externally controlling the system.
It is also applicable for upgrading IC1.
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PZ-43MR2E
PZ-50MR2E
PZ-50MR2E
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The information shown in the list is basic information and may not correspond exactly to that shown in the schematic diagrams.
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VHiCXA2069Q-1 (ASSY: IC1301)
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S2-Compatible, 7-Input/3-Ouput AV Switch
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Block Diagram
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PZ-43MR2E
PZ-50MR2E
PZ-50MR2E
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1
8
15
22
30
60
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10
17
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49
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12
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26
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62, 2
9, 16
23, 29
59, 64
4, 11
18, 25
31, 61
53
41
44
1
8
15
22
30
60
3
10
17
24
49
5
12
19
26
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62, 2
9, 16
23, 29
59, 64
4, 11
18, 25
31, 61
53
41
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39
58
47
37
52
43
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54
45
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13
20
27
7
14
21
28
32
39
58
47
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52
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54
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40
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13
20
27
7
14
21
28
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55
46
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48
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Pin Function
Pin No.
Pin Name
I/O
Pin Function
TV
V1
V2
V3
V4
V5
V6
Y1
Y2
Y3
Y4
YIN1
C1
C2
C3
C4
CIN1
LTV, LV1
LV2, LV3
LV4, LV5
LV6, RTV
RV1, RV2
RV3, RV4
RV5, RV6
VOUT1
VOUT3
V/YOUT2
V1
V2
V3
V4
V5
V6
Y1
Y2
Y3
Y4
YIN1
C1
C2
C3
C4
CIN1
LTV, LV1
LV2, LV3
LV4, LV5
LV6, RTV
RV1, RV2
RV3, RV4
RV5, RV6
VOUT1
VOUT3
V/YOUT2
YOUT1
YOUT3
COUT1
COUT2
COUT3
LOUT1
LOUT2
LOUT3
ROUT1
ROUT2
ROUT3
S2-1
S2-2
S2-3
S2-4
S-1
S-2
S-3
S-4
ADR
YOUT3
COUT1
COUT2
COUT3
LOUT1
LOUT2
LOUT3
ROUT1
ROUT2
ROUT3
S2-1
S2-2
S2-3
S2-4
S-1
S-2
S-3
S-4
ADR
SCL
SDA
DC OUT
SDA
DC OUT
TRAP1
TRAP2
MUTE
TRAP2
MUTE
BIAS
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Video signal input.
Composite video signal input
Composite video signal input
Y/C-separated signal input terminal for luminance signal input.
YIN1 to feed in the Y/C-separated signal of VOUT1 output.
YIN1 to feed in the Y/C-separated signal of VOUT1 output.
Y/C-separated signal input terminal for chrominance signal input.
CIN1 to feed in the Y/C-separated signal of VOUT1 output.
CIN1 to feed in the Y/C-separated signal of VOUT1 output.
Audio signal input terminal.
Video signal output terminal for composite video signal output.
Video signal output terminal for selection between composite video signal output and
luminance signal output by I2C Bus control.
Video signal output terminal for luminance signal output.
luminance signal output by I2C Bus control.
Video signal output terminal for luminance signal output.
Video signal output terminal for chrominance signal output.
Audio signal output terminal.
Used to detect C signal-superimposed, S2-compatible DC level. 4:3 video signal when
below 1.3V. 4:3 letterbox signal when between 1.3V and 2.5V. 16:9 image squeeze
signal when above 2.5V. To be pulled down to GDN at 100K
below 1.3V. 4:3 letterbox signal when between 1.3V and 2.5V. 16:9 image squeeze
signal when above 2.5V. To be pulled down to GDN at 100K
Ω
to produce 4:3 video
signal when open.
Used to switch between composite video and S signals. Detection results to be written
in status register. S signal when below 3.5V. Composite video signal when above 3.5V.
To be pulled up to 5V at 100K
Used to switch between composite video and S signals. Detection results to be written
in status register. S signal when below 3.5V. Composite video signal when above 3.5V.
To be pulled up to 5V at 100K
Ω
to produce composite video signal when open.
Used to select I2C Bus slave address. 90H when below 1.5V. 92H when above 2.5V.
90H also when the terminal is open.
I2C Bus signal input terminal.
I2C Bus signal input terminal.
Used to feed out S2-compatible DC level to be superimposed on COUT3 output. DC to
be superimposed by connecting to COUT3 output via a capacitor. Control to be made
by I2C Bus. S2-specified output impedance of 10 ±3K
90H also when the terminal is open.
I2C Bus signal input terminal.
I2C Bus signal input terminal.
Used to feed out S2-compatible DC level to be superimposed on COUT3 output. DC to
be superimposed by connecting to COUT3 output via a capacitor. Control to be made
by I2C Bus. S2-specified output impedance of 10 ±3K
Ω
to be realized by adding an
external resistance of 4.7K
Ω
.
Subcarrier trap circuit to be connected.
Audio signal output mute terminal. Mute off when below 1.3V. Mute on when above
2.5V. Mute off when the terminal is open.
Internal reference bias (Vcc/2) terminal. To be connected to GND with a capacitor in
between.
2.5V. Mute off when the terminal is open.
Internal reference bias (Vcc/2) terminal. To be connected to GND with a capacitor in
between.
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PZ-43MR2E
PZ-50MR2E
PZ-50MR2E
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VHiMM1519XQ-1(IC1401)
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Component Input Video Switch
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Block Diagram
