Sharp LC-52XL1E (serv.man5) Service Manual ▷ View online
LC-46XL1E/RU, LC-52XL1E/RU
5 – 9
8
EXP[15]
O
LED OPC (Light-up at “L”) (INT: “H”)
LEDOPC
9
VCCIO1 3.3V
—
Power supply 3.3V
3.3V
10
GND
—
Ground
GND
11
GND
—
Ground
GND
12
PCLK
I
Panel clock 74.25MHz
PCLK
13
VCCINT 3.3V
—
Power supply 3.3V
3.3V
14
I/O
—
GND*
NC
15
I/O
—
GND*
NC
16
I/O
—
GND*
NC
17
OSCOUT
O
Light control clock output (No lamp light-up at initial “L”)
OSCOUT
18
I/O
—
GND*
NC
19
OFLOUT
O
Light control PWM output (No lamp light-up at initial “L”)
OFL1OUT
20
OFL2OUT
O
Light control PWM output
OFL2OUT
21
I/O
—
GND*
NC
22
(TMS)
I/O
Inline Program JTAG TMS/OPEN
TMS
23
(TDI)
I/O
Inline Program JTAG DataIn/OPEN
TDI
24
(TCK)
I/O
Inline Program JTAG Clock/OPEN
TCK
25
(TDO)
O
Inline Program JTAG DataOut/OPEN
TDO
26
I/O
I
Write mode Vpp-cont
NC
27
I/O
—
GND*
NC
28
I/O
—
GND*
NC
29
I/O
—
GND*
NC
30
I/O
—
GND*
NC
31
VCCIO1 3.3V
—
Power supply 3.3V
3.3V
32
GND
—
Ground
GND
33
I/O
—
GND*
NC
34
EXP[16]
O
MSP&FRC Reset: Note 2 (INT: “L”)
RESET_A
35
EXP[17]
O
DTU-CVBS/ (S-VY
⋅ CVBS) switching (INT: “L”)
G_ONSYNC
36
EXP[18]
O
DTV/PC/HDMI switching (INT: “L”)
DTVPC
37
EXP[19]
O
DTV/PC/HDMI switching (INT: “L”)
DTVHDMI
38
EXP[20]
O
E2PROM WP for HDMI (INT: “L”)
HDMI_WP
39
EXP[21]
O
Panel flip horizontal (INT: “L”)
LCDLR
40
EXP[22]
O
Panel flip vertical (INT: “L”)
LCDUD
41
EXP[23]
O
Panel 50/60Hz (INT: “L”)
FRAME
42
I/O
—
GND*
NC
43
I/O
—
GND*
NC
44
I/O
—
GND*
NC
45
VCCIO1 3.3V
—
Power supply 3.3V
3.3V
46
GND
—
Ground
GND
47
EXP[24]
O
Common Bias Adjustment write Protect. (INT: “L”)
TCON_WP
48
EXP[25]
O
FRC_I2C_SW (INT: “L”)
FRC_I2C_SW
49
EXP[26]
O
Charge share impulse control (on/off). (INT: “L”)
CSI
50
EXP[27]
O
Pcom1.5-control (INT: “L”)
Ppcon1.5
51
EXP[28]
O
Panel Control. (INT: “L”)
BANK
52
EXP[29]
O
Not used
NC
53
EXP[30]
O
Not used
NC
54
EXP[31]
O
Reset Trigger
NC
55
I/O
—
GND*
NC
56
I/O
—
GND*
NC
57
I/O
—
GND*
NC
58
I/O
—
GND*
NC
59
VCCIO2 3.3V
—
Power supply 3.3V
3.3V
60
GND
—
Ground
GND
61
I/O
—
GND*
NC
62
GCLR
I
VGC_Reset_Line
RESET_N
63
VCCINT 3.3V
—
Power supply 3.3V
3.3V
64
SCK
I
Serial Clock (from VGC)
SCK
65
GND
—
Ground
GND
66
SEN
I
Serial Data Enable (from VGC)
FPGA_SDE
67
SDAI
I
Serial Data (from VGC)
FPGA_SDA
68
I/O
—
GND*
NC
69
SDAO
O
Serial Data Output enable (from VGC) (INT: “L”)
FPGA_SDAO
70
I/O
—
GND*
NC
71
I/O
—
GND*
NC
Pin No.
Pin Name
I/O
Pin Function
Sheet Name
LC-46XL1E/RU, LC-52XL1E/RU
5 – 10
GND*: Non-configured pins are fixed at GND.
Terminals' electrical characteristics are referred to in the EPM240T100C5N data sheet of Altera.
Note 1: Reset output monitor terminal with EXP31 in use.
Note 2: Composed of GCLR and OR.
72
I/O
—
GND*
NC
73
I/O
—
GND*
NC
74
I/O
—
GND*
NC
75
OFL2EN
I
OFL2 output enable
GND
76
I/O
—
GND*
NC
77
I/O
O
VGC soft write (Write mode at “H”) (INT: “L”)
BOOT
78
I/O
—
GND*
NC
79
GND
—
Ground
GND
80
VCCIO2 3.3V
—
Power supply 3.3V
3.3V
81
I/O
I
VSYNC_OSC
VSYNC
82
I/O
I
HSYNC_OSC
HSYNC
83
I/O
—
GND*
NC
84
I/O
—
GND*
NC
85
EXP[0]
O
Digital Tuner I2C Selector (INT: “L”)
DTI2CSEL
86
EXP[1]
O
DTM_RESET (INT: “L”)
DTM_RESET
87
EXP[2]
O
DTU_ON (Analog tuner at “L”, D-tuner at “H”) (INT: “L”)
DTU_ON
88
EXP[3]
O
232C on/off SW (RS232C action at “H”: VGC write enabled) (INT: “H”)
IREM_SW
89
EXP[4]
O
Set Top Box (LAMP ON) (INT: “L”)
STB
90
EXP[5]
O
S2_MUTE (INT: “L”)
S_2MUTE
91
EXP[6]
O
ANT+5V ON
ANT+5V ON
92
EXP[7]
O
S_MUTE (INT: “L”)
S-MUTE
93
GND
—
Ground
GND
94
VCCIO2 3.3V
—
Power supply 3.3V
3.3V
95
I/O
—
GND*
NC
96
I/O
—
GND*
NC
97
I/O
—
GND*
NC
98
I/O
—
used to TP1703
TP1703
99
I/O
—
GND*
NC
100
OFL-SET-IN
I
OFLWD[8] external setting terminal
GND
Pin No.
Pin Name
I/O
Pin Function
Sheet Name
LC-46XL1E/RU, LC-52XL1E/RU
5 – 11
7. IC1905: VHiSii9025+-1Q
HDMI RECIEVER
Pin No.
Pin Name
I/O
Pin Function
144
Q0
O
24-bit Output Pixel Data Bus. HDMI-B[0]
143
Q1
O
24-bit Output Pixel Data Bus. HDMI-B[1]
142
Q2
O
24-bit Output Pixel Data Bus. HDMI-B[2]
141
Q3
O
24-bit Output Pixel Data Bus. HDMI-B[3]
140
Q4
O
24-bit Output Pixel Data Bus. HDMI-B[4]
137
Q5
O
24-bit Output Pixel Data Bus. HDMI-B[5]
LC-46XL1E/RU, LC-52XL1E/RU
5 – 12
136
Q6
O
24-bit Output Pixel Data Bus. HDMI-B[6]
133
Q7
O
24-bit Output Pixel Data Bus. HDMI-B[7]
132
Q8
O
24-bit Output Pixel Data Bus. HDMI-G[0]
131
Q9
O
24-bit Output Pixel Data Bus. HDMI-G[1]
130
Q10
O
24-bit Output Pixel Data Bus. HDMI-G[2]
129
Q11
O
24-bit Output Pixel Data Bus. HDMI-G[3]
126
Q12
O
24-bit Output Pixel Data Bus. HDMI-G[4]
125
Q13
O
24-bit Output Pixel Data Bus. HDMI-G[5]
124
Q14
O
24-bit Output Pixel Data Bus. HDMI-G[6]
123
Q15
O
24-bit Output Pixel Data Bus. HDMI-G[7]
119
Q16
O
24-bit Output Pixel Data Bus. HDMI-R[0]
118
Q17
O
24-bit Output Pixel Data Bus. HDMI-R[1]
117
Q18
O
24-bit Output Pixel Data Bus. HDMI-R[2]
116
Q19
O
24-bit Output Pixel Data Bus. HDMI-R[3]
113
Q20
O
24-bit Output Pixel Data Bus. HDMI-R[4]
112
Q21
O
24-bit Output Pixel Data Bus. HDMI-R[5]
111
Q22
O
24-bit Output Pixel Data Bus. HDMI-R[6]
110
Q23
O
24-bit Output Pixel Data Bus. HDMI-R[7]
1
DE
O
Data enable.
2
HSYNC
O
Horizontal Sync Output control signal.
3
VSYNC
O
Vertical Syanc Output control signal.
121
ODCK
O
Output Data Clock. HDMI-CLK
97
XTALIN
I
Crystal Clock Input.
96
XTALOUT
O
Crystal Clock Output.
88
MCLKOUT
O
Audio Master Clock Output.
87
MCLKIN
I
Audio Master Clock Input Reference.
86
SCK
O
I2S Serial Clock Output.
85
WS
O
I2S Word Select Output.
84
SDO
O
I2S Serial Data Output.
78
SPDIF
O
S/PDIF Audio Output
77
MUTEOUT
O
Mute Audio Output.
104
INT
O
Interrupt Output.
102
RESET#
I
Reset Pin. Active LOW. 5V Tolerant.
32
DSCL0
I
DDC I2C Clock for Port 0. 5V Tolerant.
31
DSDA0
I/O
DDC I2C Data for Port 0. 5V Tolerant.
30
DSCL1
I
DDC I2C Clock for Port 1. 5V Tolerant.
29
DSDA1
I/O
DDC I2C Data for Port 1. 5V Tolerant.
28
CSCL
I
Configuration I2C Clock. 5V Tolerant.
27
CSDA
I/O
Configuration I2C Data. 5V Tolerant.
103
SCDT
O
Indicates active video at HDMI input port.
107
CLK48B
I/O
Data Bus Latch Enable. 2
34
R0PWR5V
I
Port 0 Transmitter Detect. 5V Tolerant.
33
R1PWR5V
I
Port 1 Transmitter Detect. 5V Tolerant.
101
TEST
I
Test Terminal.
6.7.13.19
VCC
—
VCC (3.3V)
8.12.18
GND
—
Ground
10
RSET
O
Reset Pin.
11
COMP
I
Comparator
14, 17, 20, 56,
81, 82, 83, 93,
100
81, 82, 83, 93,
100
NC
—
No internal connection.
9
EVNODD
O
Even/Odd field for interlaced modes.
40
R0XC+
I
TMDS input clock pair. HDMI Port 0.
39
R0XC-
I
TMDS input clock pair. HDMI Port 0.
44
R0X0+
I
TMDS input data pair. HDMI Port 0.
43
R0X0-
I
TMDS input data pair. HDMI Port 0.
48
R0X1+
I
TMDS input data pair. HDMI Port 0.
47
R0X1-
I
TMDS input data pair. HDMI Port 0.
52
R0X2+
I
TMDS input data pair. HDMI Port 0.
51
R0X2-
I
TMDS input data pair. HDMI Port 0.
59
R1XC+
I
TMDS input clock pair. HDMI Port 1.
58
R1XC-
I
TMDS input clock pair. HDMI Port 1.
63
R1X0+
I
TMDS input data pair. HDMI Port 1.
62
R1X0-
I
TMDS input data pair. HDMI Port 1.
67
R1X1+
I
TMDS input data pair. HDMI Port 1.
Pin No.
Pin Name
I/O
Pin Function
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