Sharp LC-50LE751K Handy Guide ▷ View online
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Major IC Information…cont
October 2013
Features…cont
Analog-to-digital converter (ADC).
Analog-to-digital converter (ADC).
o 10-bit, ±1 LSB ADC with up to 10 multiplexed channels, scan mode and analog watchdog.
I/Os.
o Up to 38 I/Os on a 48-pin package including 16 high sink outputs.
o Highly robust I/O design, immune against current injection
Unique ID.
o 96-bit unique key for each device.
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October 2013
IC8401: 2Gbit NAND FLASH
Part number: MT29F4G08ABADAWP:D (MICRON)
Sharp code: RH-IXD552WJQZQ
Sharp code: RH-IXD552WJQZQ
http://datasheet.elcodis.com/pdf2/69/78/697874/mt29f4g08abadawpd.pdf
Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These
devices use a highly multiplexed 8-bit bus (I/Ox) to transfer commands, address, and data. There are five control
signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control
hardware write protection and monitor device status (R/B#).
This hardware interface creates a low pin-count device with a standard pinout that remains the same from one
density to another, enabling future upgrades to higher densities with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND Flash die. A
NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash
die, in the ONFI specification, is referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable
signal. For further details, see Device and Array Organization.
This device has an internal 4-bit ECC that can be enabled using the GET/SET features.
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These devices use NAND Flash electrical and command interfaces. Data, commands, and addresses are
multiplexed onto the same pins and received by I/O control circuits. The commands received at the I/O
control circuits are latched by a command register and are transferred to control logic circuits for generating
internal signals to control device operations. The addresses are latched by an address register and sent to a
row decoder to select a row address or to a column decoder to select a column address. Data is transferred to
or from the NAND Flash memory array, byte by byte (x8) or word by word (x16), through a data register and a
cache register. The NAND Flash memory array is programmed and read using page-based operations and is
erased using blockbased operations. During normal page operations, the data and cache registers act as a
single register. During cache operations, the data and cache registers operate independently to increase data
throughput. The status register reports the status of die operations.
multiplexed onto the same pins and received by I/O control circuits. The commands received at the I/O
control circuits are latched by a command register and are transferred to control logic circuits for generating
internal signals to control device operations. The addresses are latched by an address register and sent to a
row decoder to select a row address or to a column decoder to select a column address. Data is transferred to
or from the NAND Flash memory array, byte by byte (x8) or word by word (x16), through a data register and a
cache register. The NAND Flash memory array is programmed and read using page-based operations and is
erased using blockbased operations. During normal page operations, the data and cache registers act as a
single register. During cache operations, the data and cache registers operate independently to increase data
throughput. The status register reports the status of die operations.
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October 2013
IC9501: Single Port 10/100 Fast Ethernet Transceiver
Part number: KSZ8081RNDTR (MICREL)
Sharp code: RH-IXD543WJZZY
Sharp code: RH-IXD543WJZZY
http://www.mouser.com/catalog/specsheets/KSZ8081RNDCA.pdf
The KSZ8081RND is a single-supply 10BaseT-100Base-TX Ethernet physical-layer transceiver for transmission and
reception of data over standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ8081 is a highly-integrated PHY solution. It reduces board cost and simplifies board layout by using on-chip
termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core, and by
offering 1.8/2.5/3.3V digital I/O interface support.
The KSZ8081RND offers the Reduced Media Independent Interface (RMII) for direct connection to RMII-compliant
MACs in Ethernet processors and switches As the power-up default, the KSZ8081RND uses a 25MHz crystal to
generate all required clocks, including the 50MHz RMII reference clock output for the MAC.
reception of data over standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ8081 is a highly-integrated PHY solution. It reduces board cost and simplifies board layout by using on-chip
termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core, and by
offering 1.8/2.5/3.3V digital I/O interface support.
The KSZ8081RND offers the Reduced Media Independent Interface (RMII) for direct connection to RMII-compliant
MACs in Ethernet processors and switches As the power-up default, the KSZ8081RND uses a 25MHz crystal to
generate all required clocks, including the 50MHz RMII reference clock output for the MAC.
Features:
Single-chip 10BaseT/100BaseTx IEEE 802.3 compliant Ethernet transceiver.
RMII v1.2 Interface support with a 50MHz reference clock output to MAC.
MDC/MDIO management interface for PHY register configuration.
Programmable interrupt output.
On-chip termination resistors for the differential pairs.
Baseline wander correction.
Single-chip 10BaseT/100BaseTx IEEE 802.3 compliant Ethernet transceiver.
RMII v1.2 Interface support with a 50MHz reference clock output to MAC.
MDC/MDIO management interface for PHY register configuration.
Programmable interrupt output.
On-chip termination resistors for the differential pairs.
Baseline wander correction.
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