Sharp LC-42XL2E (serv.man5) Service Manual ▷ View online
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 8
2.4. IC1301 (VHiYDA147SZ-1Y)
2.4.1 Block Diagram
2.4.2 Pin Connections and short description
14, 15, 16, 17,
18, 19, 20, 21,
43, 44, 45, 46,
47, 55, 56
18, 19, 20, 21,
43, 44, 45, 46,
47, 55, 56
AGND
—
Analog GND.
5, 26, 36
AVCC18
—
Analog VCC. Connect to 1.8V supply.
22, 48
DVCC18
—
Digital VCC. Connect to 1.8V supply.
23, 49
DGND
—
Digital GND.
31, 42
AVCC33
—
Analog VCC. Connect to 3.3V supply.
Pin No.
Pin Name
I/O
Pin Function
1, 2, 12, 25, 35, 36
NC
—
No connection
3
PVDDREG
—
Power terminal for regulator (PVDD)
4
AVDD
—
Output terminal for 3.3V regulator
5
INLP
I
Analog input terminal (Lch+)
6
INLM
I
Analog input terminal (Lch-)
7
VREF
VREF terminal
8
INRM
I
Analog input terminal (Rch-)
9
INRP
I
Analog input terminal (Rch+)
10
AVSS
—
GND terminal for analog
11
PLIMIT
I
Power limit setting terminal
13, 14
PVDDPR
—
Power terminal for digital amplifier output (Rch+)
Pin No.
Pin Name
I/O
Pin Function
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 9
2.5. IC1402 (VHiR2S15502-1Y)
2.5.1 Pin Connections and short description
15, 16, 17
OUTPR
O
Digital amplifier output terminal (Rch+)
18, 19
PVSSR
—
Ground terminal for digital amplifier output (Rch)
20, 21, 22
OUTMR
O
Digital amplifier output terminal (Rch-)
23, 24
PVDDMR
—
Power terminal for digital amplifier output (Rch-)
26
SLEEPN
I
Sleep control terminal
27
PROTN
O
Error flag output terminal
28
MUTEN
I
Mute control terminal
29
CKOUT
O
Clock output terminal for synchronization
30
CKIN
I
External clock input terminal
31
NCDRC0
I
Non-clip/DRC1/DRC2 mode selection terminal 0
32
NCDRC1
I
Non-clip/DRC1/DRC2 mode selection terminal 1
33
GAIN0
I
GAIN setting terminal 0
34
GAIN1
I
GAIN setting terminal 1
37, 38
PVDDML
—
Power terminal for digital amplifier output (Lch-)
39, 40, 41
OUTML
O
Digital amplifier output terminal (Lch-)
42, 43
PVSSL
—
Ground terminal for digital amplifier output (Lch)
44, 45, 46
OUTPL
O
Digital amplifier output terminal (Lch+)
47, 48
PVDDPL
—
Power terminal for digital amplifier output (Lch+)
Pin No.
Pin Name
I/O
Pin Function
1
AVSS
—
0V Power Supply for Analog Core
2
AVDD
—
3.3V Power Supply for Analog Core
3
SIF
I
Sound IF Input
4
VREF1
—
ADC Voltage Reference 1
5
VREF2
—
ADC Voltage Reference 2
6
TEST
I
Test pin
7
XI
I
Crystal Oscillator Input
8
XO
O
Crystal Oscillator Output
9
IVDD
—
3.3V Power Supply for I/O Buffer
10
IVSS
—
0V Power Supply for I/O Buffer
11
DVSS
—
0V Power Supply for Logic Core
12
DVDD
—
1.5V Power Supply for Logic Core
13
DACCLK
I/O
DAC Clock
14
BCK
I/O
Bit Clock
15
LRCK
I/O
LR Clock
16
SD0
O
Digital Output for External DAC
17
SDI
I
Digital Input for Internal DAC
18
SDA
I/O
I2C bus Serial Data
19
SCL
I
I2C bus Serial Clock
20
STATUS
I/O
PLL Setting / Status Signal
21
RESET
I
Hardware Reset (Active low)
22
ROUT
O
Rch Analog Output
23
VCOM
—
DAC Voltage Reference
24
LOUT
O
Lch Analog Output
Pin No.
Pin Name
I/O
Pin Function
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 10
2.6. IC1403 (VHiTAS3108D-1Y)
2.6.1 Block Diagram
2.6.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
38
AVDD
—
Analog power-supply input (3.3V)
1
AVSS
—
Analog ground
7
CS0
I
Pull-down Chip select
9, 30
DVDD
—
Digital power-supply input (3.3V)
10, 29
DVSS
—
Digital ground
8
GPIO
I/O
Pull-up GPIO control pin (user programmable)
19
LRCLK
I/O
Pull-down Sample rate clock (fS) input or output
5
MCLKIN
I
Master clock input (Connect to ground when not in use.)
21
MCLKO
O
Master clock output
6
MICROCLK_DIV
I
Pull-down Internal microprocessor clock divide control
31
PDN
I
Pull-up Powers down all logic and stops all clocks, active-low. Coefficient memory remains stable
through power-down cycle.
through power-down cycle.
34
PLL0
I
Pull-up PLL control 0
35
PLL1
I
Pull-down PLL control 1
36
PLL2
I
Pull-down PLL control 2
33, 37
RESERVED
—
Connect to ground
32
RESET
I
Pull-up Reset, active-low
16
SCL1
I/O
I2C port #1 clock (always a slave)
18
SCL2
I/O
I2C port #2 clock (always a slave)
20
SCLKIN
I
Pull-down Bit clock input
LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU
5 – 11
2.7. IC1404 (VHiAK4683EQ-1Q)
2.7.1 Block Diagram
22
SCLKOUT1
O
Bit clock #1 out. Used to receive input serial data.
23
SCLKOUT2
O
Bit clock #2 out. Used to clock output serial data.
15
SDA1
I/O
I2C port #1 data (always a slave)
17
SDA2
I/O
I2C port #2 data (always a slave)
11
SDIN1
I
Pull-down Serial data input 1
12
SDIN2
I
Pull-down Serial data input 2
13
SDIN3
I
Pull-down Serial data input 3
14
SDIN4
I
Pull-down Serial data input 4
27
SDOUT1
O
Serial data output 1
26
SDOUT2
O
Serial data output 2
25
SDOUT3
O
Serial data output 3
24
SDOUT4
O
Serial data output 4
2
VR_PLL
—
Internal regulator. This pin must not be used to power external devices.
3
XTALI
I
Oscillator input (connect to ground when not in use)
4
XTALO
O
Oscillator output
28
VR_DIG
---
Internal regulator. This pin must not be used to power external devices.
Pin No.
Pin Name
I/O
Pin Function
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