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LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU

5 – 6

49

DCOUT

O

DC output for S-terminal.

51

VOUT3

O

Monitor output (composit signal)

50

COUT3/VOUT6

O

Monitor output (Chroma or composite signal)

52

YOUT3/ VOUT5

O

Monitor output (Luminance or composite signal)

54

PROUT2

O

Colour difference PR-signal output.

58

PROUT1

O

55

PBOUT2/ COUT2

O

Colour difference PB-signal or chroma signal output.

59

PBOUT1/ COUT1

O

56

CYOUT2/ YOUT2/ VOUT2

O

Colour difference signal, Luminance or composite signal output.

60

CYOUT1/ YOUT1/ VOUT1

O

64

O1

O

Output port.

66

O2

O

72

O3

O

78

O4

O

53, 57

VDD1

—

Power supply (+9V)

8, 47

VDD2

—

Power supply (+5V)

18, 44, 62

GND

—

Ground

4, 6, 10, 11, 12, 13, 
17, 19, 39, 41, 43, 
48, 61, 63

NC

—

Unconnected pins.

LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU

5 – 7

37

DSDA

I/O

DDC I2C Data for respective port. 

38

DSCL

I

DDC I2C Clock.

39

RPWR

I

5V Port detection input. Connect to 5V signal from HDMI input connector.

25

HPD

O

Hot Plug Detect Output. Connect to HOTPLUG of HDMI input connector.

51

HPDIN

I

Hot Plug Detect Input.

53

TSCL

O

Master DDC I2C Clock (Open Drain Output) to HDMI receiver.
I2C transactions required for HDCP operation are performed over this I2C bus.

52

TSDA

I/O

Master DDC Data (Open drain output.) to HDMI receiver.
I2C transactions required for HDCP operation are performed over this I2C bus.

Configuration
54

I2CADDR/TPWR

I/O

I2C Slave Address input/Transmit Power Sense output pin.
When RESET# is low, this pin is used as an input to latch the I2C sub-address.
The level on this pin is latched when the RESET# pin transitions from low to high.
When RESET# is high, this pin is used as the TPWR output, indicating that the Rx-port has 5V 
present.

24

I2CSEL/INT#

I/O

I2C Selection input/ Interrupt output pin.
The SiI9181 has two modes of operation: Local I2C control and Standalone.
The mode is determined by the level of the I2CSEL/INT pin at the rising edge of RESET#.
A high indicates I2C mode, and a low indicates Standalone mode.
In Local I2C mode, all functions are controlled and observed with I2C registers using the pins 
LSCL/EPSEL1 and LSDA/EPSEL0 as the local I2C bus.
In Standalone mode, the external pins LSCL/ EPSEL1 and LSDA/ EPSEL0 are use to determine 
whether the SiI9181 is in Normal mode or Standby mode.
After reset, this pin becomes the Interrupt output.
This is an open-drain output and requires an external pull-up.

50

RSVDL

—

Reserved for use by Silicon Image and must be tied low.

Control Pins
11

RESET#

I

Reset Pin (Active LOW). Certain configuration inputs are latched when RESET# transitions from 
low to high.

13

LSCL/EPSEL1

I

Local I2C Clock / External Port Select 1. When I2CSEL is high, this becomes the Local I2C bus 
clock pin, LSCL. When I2CSEL is low, this becomes the external port select pin, EPSEL1.
True open drain, so does not pull to ground if power not applied.
An external pull-up is required.

12

LSDA/EPSEL0

I/O

Local I2C Data / External Port Select 0. When I2CSEL is high, this becomes the Local I2C bus 
data pin, LSDA. When I2CSEL is low, this becomes the external port select pin, EPSEL0.
True open drain, so does not pull to ground if power not applied.
An external pull-up is required.

CEC Pins
41

CEC_A

I/O

HDMI compliant CEC I/O used to interface to CEC devices.
CEC electrically compliant signal. This pin connects to the CEC signal of all HDMI connectors in 
the system.
As an input, the pad acts as a LVTTL Schmitt triggered input and is 5V tolerant. As an output, the 
pad acts as an NMOS driver with resistive pull-up. This pin has an internal pull-up resistor.

40

CEC_D

I/O

CEC interface to local system. True open-drain. An external pull-up is required. This pin typically 
connects to the local CPU.

Differential Signal Data Pins
30

RX0+

I

TMDS input data pairs.

29

RX0-

I

33

RX1+

I

32

RX1-

I

35

RX2+

I

34

RX2-

I

28

RXC+

I

TMDS input clock pair.

27

RXC-

I

6

TX0+

O

TMDS output data pairs.

7

TX0-

O

3

TX1+

O

4

TX1-

O

1

TX2+

O

2

TX2-

O

8

TXC+

O

TMDS output clock pair.

9

TXC-

O

10

EXT_SWING

O

Voltage Swing Adjust. A resistor tied from this pin to AVCC18 determines the amplitude of the volt-
age swing. The recommended value is 750 

Ω.

LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU

5 – 8

14, 15, 16, 17, 
18, 19, 20, 21, 
43, 44, 45, 46, 
47, 55, 56

AGND

—

Analog GND.

5, 26, 36

AVCC18

—

Analog VCC. Connect to 1.8V supply.

22, 48

DVCC18

—

Digital VCC. Connect to 1.8V supply.

23, 49

DGND

—

Digital GND.

31, 42

AVCC33

—

Analog VCC. Connect to 3.3V supply.

1, 2, 12, 25, 35, 36

NC

—

No connection

3

PVDDREG

—

Power terminal for regulator (PVDD)

4

AVDD

—

Output terminal for 3.3V regulator

5

INLP

I

Analog input terminal (Lch+)

6

INLM

I

Analog input terminal (Lch-)

7

VREF

VREF terminal

8

INRM

I

Analog input terminal (Rch-)

9

INRP

I

Analog input terminal (Rch+)

10

AVSS

—

GND terminal for analog

11

PLIMIT

I

Power limit setting terminal

13, 14

PVDDPR

—

Power terminal for digital amplifier output (Rch+)

LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU

5 – 9

15, 16, 17

OUTPR

O

Digital amplifier output terminal (Rch+)

18, 19

PVSSR

—

Ground terminal for digital amplifier output (Rch)

20, 21, 22

OUTMR

O

Digital amplifier output terminal (Rch-)

23, 24

PVDDMR

—

Power terminal for digital amplifier output (Rch-)

26

SLEEPN

I

Sleep control terminal

27

PROTN

O

Error flag output terminal

28

MUTEN

I

Mute control terminal

29

CKOUT

O

Clock output terminal for synchronization

30

CKIN

I

External clock input terminal

31

NCDRC0

I

Non-clip/DRC1/DRC2 mode selection terminal 0

32

NCDRC1

I

Non-clip/DRC1/DRC2 mode selection terminal 1

33

GAIN0

I

GAIN setting terminal 0

34

GAIN1

I

GAIN setting terminal 1

37, 38

PVDDML

—

Power terminal for digital amplifier output (Lch-)

39, 40, 41

OUTML

O

Digital amplifier output terminal (Lch-)

42, 43

PVSSL

—

Ground terminal for digital amplifier output (Lch)

44, 45, 46

OUTPL

O

Digital amplifier output terminal (Lch+)

47, 48

PVDDPL

—

Power terminal for digital amplifier output (Lch+)

1

AVSS

—

0V Power Supply for Analog Core

2

AVDD

—

3.3V Power Supply for Analog Core

3

SIF

I

Sound IF Input

4

VREF1

—

ADC Voltage Reference 1

5

VREF2

—

ADC Voltage Reference 2

6

TEST

I

Test pin

7

XI

I

Crystal Oscillator Input

8

XO

O

Crystal Oscillator Output

9

IVDD

—

3.3V Power Supply for I/O Buffer

10

IVSS

—

0V Power Supply for I/O Buffer

11

DVSS

—

0V Power Supply for Logic Core

12

DVDD

—

1.5V Power Supply for Logic Core

13

DACCLK

I/O

DAC Clock

14

BCK

I/O

Bit Clock

15

LRCK

I/O

LR Clock

16

SD0

O

Digital Output for External DAC

17

SDI

I

Digital Input for Internal DAC

18

SDA

I/O

I2C bus Serial Data

19

SCL

I

I2C bus Serial Clock

20

STATUS

I/O

PLL Setting / Status Signal

21

RESET

I

Hardware Reset (Active low)

22

ROUT

O

Rch Analog Output

23

VCOM

—

DAC Voltage Reference

24

LOUT

O

Lch Analog Output