DOWNLOAD Sharp LC-42XL2E (serv.man5) Service Manual ↓ Size: 2.32 MB | Pages: 42 in PDF or view online for FREE

LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU

5 – 2

Sil9185 is a 3-input/1-output switch compatible with HDMI1.3.

• Built in Consumer Electronics Control (CEC) support

• Individual control of Hot Plug Detect (HPD) for each port

• 5V detect to help speed soft mute of audio during plug-in, plug-out conditions

• Control via local I2C bus.

• Supports video resolutions up to 1080p, 60Hz, 12-bit or 720p/1080i, 120Hz, 12-bit

• Built-in adaptive equalizer provides long cable support even at deep color resolutions

• Pre-emphasis in transmitter

• DVI 1.0, HDCP 1.1 and HDMI 1.3 compliant receiver and transmitter

Single output, Single input HDMI buffer.

• Built in Consumer Electronics Control (CEC) support

• Control of the Hot Plug Detect (HPD) signal

• 5V detect to help speed soft mute of audio during plug-in, plug-out conditions

• Control via local I2C bus.

• Supports video resolutions up to 1080p, 60Hz, 12-bit or 720p/1080i, 120Hz, 12-bit

• Built-in adaptive equalizer provides long cable support even at deep color resolutions

• Pre-emphasis in transmitter

• DVI 1.0, HDCP 1.1 and HDMI 1.3 compliant receiver and transmitter

This IC performs the CPLD (Complex Programmable Logic Device) RESET, I/O and Bus control.

HIDTVPro-LX Digital AV decoder & Main CPU.

• Master CPU with MMU.

• DDR2 memory up to 256mHz.

• Two Transport stream inputs, DVB compliant.

• Two HD MPEG2 video decoders.

• Demux, supports two TS inputs and one PS input.

• DVB_CI, up to two PCMCIA slots for CAM cards.

• DVB/DES.

• AC3/MPEG2/MP3/AAC 

⋅ ⋅ ⋅ audio.

• 1920 x 1080p de-interlacing.

• Graphics engine.

• Two video planes and graphics planes with Alpha blender, overlay, scrolling, flashing, colour key, ARB support.

• Smart-Cards/UART/infrared IR/RTC/two HW timers/interrupt/Key button ADCs.

• Flash/IDE/PCI Host.

• Audio interface: AC97 link/I2S_out/I2S_in/SPDIF and lip-sync.

• Digital 24-bit RGB/YUV inputs.

• Dual port/Single port LVDS output.

• USB2.0 HOST/PHY built with EHCI.

• CVBS/S-video/YCbCr output.

• Two HD, 1920 x 1080p.

128Mbit Flash memory.

3.0V single power supply, page mode flash memory. It memorizes the program and broadcast data area.

LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU

5 – 3

The ICS275 field programmable VCXO clock synthesizer generates up to four high-quality, high-frequency clock outputs including multiple reference
clocks from a low-frequency crystal input. Using ICS’ VersaClockTM software to configure PLLs and outputs, the ICS275 contains a One-Time Pro-
grammable (OTP) ROM for field programmability. Programming features include VCXO, eight selectable configuration registers and up to two sets of
two low-skew outputs.

Using Phase-Locked Loop (PLL) techniques, the device runs from a standard fundamental mode, inexpensive crystal, or clock. 

4M x 16Bit x 4 Banks graphic DDR2 Synchronous DRAM with Differential Data Strobe.

Program, DTV video buffer.

SVP-WX Video Processor.

• Integrated HDMI Receiver

• Integrated De-interlacing

• Integrated ADC

• SRC (Scan Rate Conversion) Improvement

• PC Auto Tune

• Built-in LVDS Transmitter

• Scaling Engine

• DNR-Digital Noise Reduction Filter

• Advanced Chroma Processing

• Color Management

• RCR (Real Color Reproducer)

• Dynamic Contrast Improvement

• Integrated 3D Digital Comb Video Decoder with Programmable Filter

• Inverse Color Space Conversion (ICSC)

• Frame Rate Conversion

• Fast Blank

• Built-in ADC to decode one FB and two FS signals to support dual SCART solutions

• Teletext

• Memory Interface

• DCR Advanced Image Processing

• Multi Screen Display Mode

• OSD and VBI/Closed Caption

• Advanced OSD Engine

1M x 32Bit x 4 Banks Double Data Rate Synchronous DRA with Bi-directional Data Strobe and DLL.

Video buffer.

The monitor microprocessor is intended to communicate with the main microprocessor and to operate the system. It also controls power of the entire
system.

Transition-mode PFC (Power Factor Corrector) controller.

The PFC circuit is adopted to improve the power factor of electricity and total harmonic distortion (THD).

• Realised in BCD (Bipolar-CMOS-DMOS) technology.

• Transition-mode control of Pre-Regulators.

• Proprietary multiplier design for minimum THD (Total Harmonic Distortion) of AC input current.

• Very precise adjustable output Over-voltage protection.

LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU

5 – 4

Enhanced, Energy Efficient, Low Power Off-line Switcher.

It supplies a power supply voltage of BU5V.

• Fully integrated auto restart for short circuit and open loop fault protection saves external component costs

• Built-in circuitry practically eliminates audible noise with ordinary varnished transformer

• Programmable line under voltage detect feature prevents power on/off glitches saves external components

• Frequency jittering dramatically reduces EMI (~10 dB)- minimizes EMI filter component costs

High voltage resonant controller.

It supplies power supply voltages of INV60V/S15V/UR15V/PNL12V.

• High voltage rail up to 600V.

• CMOS shut down input.

• Under voltage lock out.

• Soft start frequency sgifting timming.

• Sense OP AMP for closed loop control or protection features.

• High accuracy current controlled oscillator.

• Integrated bootstrap diode.

• Clamping ON Vs.

LC-42XL2E/S/RU, LC-46XL2E/S/RU, LC-46X20E/S/RU, LC-52XL2E/S/RU, LC-52X20E/S/RU

5 – 5

1

RT

—

Timing resistor external terminal

2

CT

—

Timing capacitor external terminal

3

ENB

I

Control input terminal

4

GD

O

Gate drive output terminal

5

VCC

—

Power terminal

6

GND

—

Ground terminal

7

COMP

O

Error amplifier output terminal

8

FB

I

Error amplifier inversion input terminal

69

C1

I

Chroma signal input

75

C2

I

1

C3

I

7

C4

I

70

S1

I

The terminal which detects the connection state of S-connector.

76

S2

I

2

S3

I

65

V1

I

Composite signal input.

71

V2

I

77

V3

I

3

V4

I

9

V5

I

15

V6

I

68

S2-1

I

The terminal which detects the aspect ratio information of S-connector.

74

S2-2

I

80

S2-3/ FS3

I

The terminal which detects the aspect ratio information of S-connector, or which detects 
the voltage of FS pin of a scart connector.

67

Y1

I

Luminance signal input.

73

Y2

I

79

Y3

I

5

Y4

I

14

ADR

I

Slave address select pin.

16

BIAS

I

BIAS

32

L13

I

The terminal which detects the number of scanning lines information on D-connector.

20

L11/ FS1

I

The terminal which detects the number of scanning lines information on D-connector, or 
which detects the voltage of FS pin of a scart connector.

26

L12/ FS2

I

21

CY1

I

Component Y-signal input.

27

CY2

I

33

CY3

I

22

L21

I

The terminal which detects the I/P information of D-connector.

28

L22

I

34

L23

I

24

L31

I

The terminal which detects the aspect ratio information of D-connector.

30

L32

I

36

L33

I

23

PB1

I

Colour difference PB-signal input.

29

PB2

I

35

PB3

I

25

PR1

I

Colour difference PR-signal input.

31

PR2

I

37

PR3

I

38

SW1

I

The terminal which detects the connection state of D-connector.

40

SW2

I

42

SW3

I

45

SDA

I/O

Data I/O of I2C bus

46

SCL

I

Clock input of I2C bus