Sharp LC-42XD1EA (serv.man5) Service Manual ▷ View online
LC-42XD1EA/RUA
5 – 5
125
Q13
O
24-bit Output Pixel Data Bus. HDMI-G[5]
124
Q14
O
24-bit Output Pixel Data Bus. HDMI-G[6]
123
Q15
O
24-bit Output Pixel Data Bus. HDMI-G[7]
119
Q16
O
24-bit Output Pixel Data Bus. HDMI-R[0]
118
Q17
O
24-bit Output Pixel Data Bus. HDMI-R[1]
117
Q18
O
24-bit Output Pixel Data Bus. HDMI-R[2]
116
Q19
O
24-bit Output Pixel Data Bus. HDMI-R[3]
113
Q20
O
24-bit Output Pixel Data Bus. HDMI-R[4]
112
Q21
O
24-bit Output Pixel Data Bus. HDMI-R[5]
111
Q22
O
24-bit Output Pixel Data Bus. HDMI-R[6]
110
Q23
O
24-bit Output Pixel Data Bus. HDMI-R[7]
1
DE
O
Data enable.
2
HSYNC
O
Horizontal Sync Output control signal.
3
VSYNC
O
Vertical Syanc Output control signal.
121
ODCK
O
Output Data Clock. HDMI-CLK
97
XTALIN
I
Crystal Clock Input.
96
XTALOUT
O
Crystal Clock Output.
88
MCLKOUT
O
Audio Master Clock Output.
87
MCLKIN
I
Audio Master Clock Input Reference.
86
SCK
O
I2S Serial Clock Output.
85
WS
O
I2S Word Select Output.
84
SDO
O
I2S Serial Data Output.
78
SPDIF
O
S/PDIF Audio Output
77
MUTEOUT
O
Mute Audio Output.
104
INT
O
Interrupt Output.
102
RESET#
I
Reset Pin. Active LOW. 5V Tolerant.
32
DSCL0
I
DDC I2C Clock for Port 0. 5V Tolerant.
31
DSDA0
I/O
DDC I2C Data for Port 0. 5V Tolerant.
30
DSCL1
I
DDC I2C Clock for Port 1. 5V Tolerant.
29
DSDA1
I/O
DDC I2C Data for Port 1. 5V Tolerant.
28
CSCL
I
Configuration I2C Clock. 5V Tolerant.
27
CSDA
I/O
Configuration I2C Data. 5V Tolerant.
103
SCDT
O
Indicates active video at HDMI input port.
107
CLK48B
I/O
Data Bus Latch Enable. 2
34
R0PWR5V
I
Port 0 Transmitter Detect. 5V Tolerant.
33
R1PWR5V
I
Port 1 Transmitter Detect. 5V Tolerant.
101
TEST
I
Test Terminal.
6.7.13.19
VCC
-
VCC(3.3V)
8.12.18
GND
-
Ground
10
RSET
O
Reset Pin.
11
COMP
I
Comparator
14,17,20,56,81,82,
83,93,100
NC
-
No internal connection.
9
EVNODD
O
Even/Odd field for interlaced modes.
40
R0XC+
I
TMDS input clock pair. HDMI Port 0.
39
R0XC-
I
TMDS input clock pair. HDMI Port 0.
44
R0X0+
I
TMDS input data pair. HDMI Port 0.
43
R0X0-
I
TMDS input data pair. HDMI Port 0.
48
R0X1+
I
TMDS input data pair. HDMI Port 0.
47
R0X1-
I
TMDS input data pair. HDMI Port 0.
52
R0X2+
I
TMDS input data pair. HDMI Port 0.
51
R0X2-
I
TMDS input data pair. HDMI Port 0.
59
R1XC+
I
TMDS input clock pair. HDMI Port 1.
58
R1XC-
I
TMDS input clock pair. HDMI Port 1.
63
R1X0+
I
TMDS input data pair. HDMI Port 1.
62
R1X0-
I
TMDS input data pair. HDMI Port 1.
67
R1X1+
I
TMDS input data pair. HDMI Port 1.
66
R1X1-
I
TMDS input data pair. HDMI Port 1.
71
R1X2+
I
TMDS input data pair. HDMI Port 1.
70
R1X2-
I
TMDS input data pair. HDMI Port 1.
22,23,35,74,79,92,
105,114,128,139
CVCC18
-
Digital Logic VCC. (1.8V)
21,24,36,73,80,91,
106,115,127,138
CGND
-
Digital Logic GND.
5,16,26,76,89,109,
122,134
IOVCC
-
Input/Output Pin VCC. (3.3V)
LC-42XD1EA/RUA
5 – 6
3. IC4203: RH-IXC100WJZZ
16Mbit Flash Memory
4,15,25,75,90,108,
120,135
IOGND
-
Input/Output Pin GND.
38,42,46,50,57,61,
65,69
AVCC
-
TMDS Analog VCC. (3.3V)
41,45,49,53,60,64,
68,72
AGND
-
TMDS Analog GND.
37
PVCC0
-
TMDS Port 0 PLL VCC. (3.3V)
55
PVCC1
-
TMDS Port 1 PLL VCC. (3.3V)
54
TMDSPGND
-
TMDS PLL GND.
94
AUDPVCC18
-
ACR PLL VCC. (1.8V)
95
AUDPGND
-
ACR PLL GND.
98
XTALVCC
-
ACR PLL Crystal Input VCC. (3.3V)
99
REGVCC
-
ACR PLL Regulator VCC. (3.3V)
Pin No.
Pin Name
I/O
Pin Function
1-9, 16-25, 48
A0-A19
I
Address Inputs
29, 31, 33, 35, 38, 40, 42, 44 DQ0-DQ7
I/O
Data Inputs/Outputs.
30, 32, 34, 36, 39, 41, 43
DQ8-DQ14
I/O
Data Inputs/Outputs.
45
DQ15A-1
I/O
Data Input/Output or Address Input.
26
E
I
Chip Enable.
LC-42XD1EA/RUA
5 – 7
4. IC201: VHITDA9886+-1
IF-PLL DEMODULATORS
28
G
I
Output Enable
11
W
I
Write Enable.
12
RP
I
Reset/Block Temporary Unprotect
15
RB
O
Read/Busy Output.
47
BYTE
I
Byte/Word Organization Select.
37
Vcc
-
Supply Voltage.
27, 46
Vss
-
Ground.
10, 13, 14
N.C.
-
Not Connected Internally.
Pin No.
Pin Name
I/O
Pin Function
1
VIF1
I
VIF differential input 1
2
VIF2
I
VIF differential input 2
3
OP1
O
Output port 1;open-collector.
4
FMPLL
I
FM-PLL for loop filter.
5
DEEM
O
De-emphasis output for capacitor.
6
AFD
I
AF decoupling input for capacitor
7
DGND
-
Digital ground.
8
AUD
O
audio output.
9
TOP
I
tuner AGC TakeOver Pint (TOP) for resistor adjustment.
10
SDA
I/O
I2C-bus data input and output.
11
SCL
I
I2C-bus clock input.
12
SIOMAD
O
sound intercarrier output and MAD select with resistor.
13
N.C.
-
not connected.
14
TAGC
O
tuner AGC output.
15
REF
I
4 MHz crystal or reference signal input.
16
VAGC(1)
I
VIF-AGC for capacitor.
17
CVBS
O
composite video output.
18
AGND
-
analog ground.
19
VPLL
I
VIF-PLL for loop filter.
LC-42XD1EA/RUA
5 – 8
5. IC202: RH-IXB964WJZZ
DVB-T RECEIVER
20
VP
-
supply voltage.
21
AFC
O
AFC output.
22
OP2
O
output port 2; open-collector.
23
SIF1
I
SIF differential input 1 and MAD select with resistor.
24
SIF2
I
SIF differential input 2 and MAD select with resistor.
Pin No
Pin Name
I/O
Description
32
NOT_RESET
I
Hardware reset, active Low.
15
XTAL_I
I
Crystal oscillator input/external clock(2.5V)
14
XTAL_O
O
Crystal oscillator output.
1
RF_LEVEL
I
ADC 8 input for RF level monitoring.
3
QP
I
Positive Q analog input for beaseband configuration,
4
QM
I
Nagative Q analog input for baseband configuration.
5
VDDA_ISO
-
Analog ISO neutral polarization.
7
REFP
-
Internal positive reference.
8
REFM
-
Internal negative reference.
9
INCM
-
Internal common mode.
10
IM
I
Negative 1 analog input for IF and baseband configuration.
11
IP
I
Positive 1 analog input for IF and baseband configuration.
12
VDDA_1V0
-
Analog supply (1.0V)
29
SDA
I/O
Serial data (open drain)
30
SCL
I
Serial clock (open drain)
21
SDAT
I/O
SDA tuner (open drain)
20
SCLT
I
SCL tuner.
43
D7
O
Serial MPEG data or parallel MPEG data (bit 7)
42
D6
O
Parallel MPEG data (bit 6)
40
D5
O
Parallel MPEG data (bit 5)
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