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LC-32RD2E/RU, LC-37RD2E/RU

6 – 6

1

VSSD

Negative digital supply voltage; heat spreader

2

VSSA

Negative analog supply voltage

3

INN

Inverting input

4

INP

Non inverting input

5

VDDA

Positive analog supply voltage

6

POWERUP

Power-up input

7

ENABLE

Enable input

8

DIAG

Diagnostic output

9

CGND

Control ground; reference ground for pins POWERUP, ENABLE and DIAG

10

VSSD

Negative digital supply voltage; heat spreader

11

VSSD

Negative digital supply voltage; heat spreader

12

OVP

Overvoltage protection reference input

13

HVP

Half supply voltage output for charging SE capacitor

14

STABI

Decoupling of internal stabilizer

15

VSSP

Negative power supply voltage

16

OUT

PWM output

17

BOOT

Bootstrap capacitor connection

18

VDDP

Positive power supply voltage

19

HVPI

Half supply voltage output for reference voltage of input circuitry

20

VSSD

Negative digital supply voltage; heat spreader

LC-32RD2E/RU, LC-37RD2E/RU

6 – 7

1

BS

I

Boot strap. This capacitor is needed to drive the power switch's gate above the supply voltage.
It is connected between the SW and BS pins to from a floating supply across the power switch driver.

2

IN

I

Supply Voltage. The MP1415 operates from a +4.75V to +18V unregulated input.

3

SW

O

Switch. This connects the inductor to either IN through M1 or to GND through M2.

4

GND

—

Ground. This pin is the voltage reference for the regulated output voltage.
For this reason care must be taken in its layout.

5

FB

I

Feedback. An external resistor divider from the output to GND, tapped to the FB pin, sets the output voltage. 
To prevent current limit runaway during a short circuit fault condition the frequency fold back comparator low-
ers the oscillator frequency when the FB voltage is below 400mV.

6

COMP

I

Compensation. The node is the output of the output of the transconductance error amplifier and the input to 
the current comparator.

7

EN

I

Enable/UVLO. A voltage greater than 2.62V enables operation. Leave EN unconnected if unused.
An Under Voltage Lockout (UVLO) function can be implemented by the addition of a resistor divider from Vin 
to GND. For complete low current shutdown the EN pin voltage needs to be less than 700mV.

8

SS

—

Soft-start. Connect SS to an external capacitor to program the soft-start. If unused, leave it open.

LC-32RD2E/RU, LC-37RD2E/RU

6 – 8

Digital Video Output Pins
144, 143, 142, 141, 140, 137, 
136, 133, 132, 131, 130, 129, 
126, 125, 124, 123, 119, 118, 117, 
116, 113, 112, 111, 110

Q0-23

O

24-bit Output Pixel Data Bus

1

DE

O

Data enable

2

HSYNC

O

Horizontal Sync Output control signal

3

VSYNC

O

Vertical Sync Output control signal

121

ODCK

O

Output Data Clock

Digital Audio Output Pins
97

XTALIN

I

Crystal Clock Input

96

XTALOUT

O

Crystal Clock Output

88

MCLKOUT

O

Audio Master Clock Output

86

SCK

O

I2S Serial Clock Output

85

WS

O

I2S Word Select Output

84

SD0

O

I2S Serial Data Output

78

SPDIF

O

S/PDIF Audio Output

77

MUTEOUT

O

Mute Audio Output

Configuration/Programming Pins
104

INT

O

Interrupt Output

102

RESET#

I

Reset Pin. Active LOW. 5 V Tolerant

32

DSCL0

I

DDCI2C Clock for Port 0. 5 V Tolerant

31

DSDA0

I/O

DDCI2C Data for Port 0. 5 V Tolerant

30

DSCL0

I

DDCI2C Clock for Port 1. 5 V Tolerant

29

DSDA1

I/O

DDCI2C Data for Port 1. 5 V Tolerant

LC-32RD2E/RU, LC-37RD2E/RU

6 – 9

28

CSCL

I

Configuration I2C Clock. 5 V Tolerant

27

CSDA

I/O

Configuration I2C Data. 5 V Tolerant

103

SCDT

O

Indicates active video at HDMI input port

107

CLK48B

I/O

Data Bus Latch Enable

34

R0PWR5V

I

Port 0 Transmitter Detect. 5V Tolerant

33

R1PWR5V

I

Port 1 Transmitter Detect. 5V Tolerant

101

RSVDL

I

Reserved, must be tied LOW

56

RSVD_A

Reserved Pin, leave unconnected

6, 7, 8, 10, 11, 12, 13, 14, 17, 18, 
19, 20, 81, 82, 83, 87, 93, 100

NC

No internal connection

9

EVNODD

O

Indicates. Even or Odd field for interlaced formats. Polarity programmable in register

Differential Signal Data Pins
40

R0XC+

I

HDMI Port 0. TMDS input clock pair

39

R0XC-

I

44

R0X0+

I

HDMI Port 0. TMDS input data pair

43

R0X0-

I

48

R0X1+

I

HDMI Port 0. TMDS input data pair

47

R0X1-

I

52

R0X2+

I

HDMI Port 0. TMDS input data pair

51

R0X2-

I

59

R1XC+

I

HDMI Port 1. TMDS input clock pair

58

R1XC-

I

63

R1X0+

I

HDMI Port 1. TMDS input data pair

62

R1X0-

I

67

R1X1+

I

HDMI Port 1. TMDS input data pair

66

R1X1-

I

71

R1X2+

I

HDMI Port 1. TMDS input data pair

70

R1X2-

I

Power and Ground Pins
22, 23, 35, 74, 79, 92, 105, 114, 
128, 139

CVCC18

—

Digital Logic VCC

21, 24, 36, 73, 80, 91, 106, 115, 
127, 138

CGND

—

Digital Logic GND

5, 16, 26, 76, 89, 109, 122, 134

IOVCC

—

Input/Output Pin Supply (3.3V)

4, 15, 25, 75, 90, 108, 120, 135

IOGND

—

Input/Output Pin Ground

38, 42, 46, 50, 57, 61, 65, 69

AVCC

—

TMDS Analog VCC

41, 45, 49, 53, 60, 64, 68, 72

AGND

—

TMDS Analog GND

37

PVCC0

—

TMDS Port 0 PLL VCC

55

PVCC1

—

TMDS Port 1 PLL VCC

54

TMDSPGND

—

TMDS PLL GND

94

AUDPVCC18

—

ACR PLL VCC

95

AUDPGND

—

ACR PLL GND

98

XTALVCC

—

ACR PLL Crystal Input VCC

99

REGVCC

—

ACR PLL Regulator VCC