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Model
LC-37P55E (serv.man12)
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24
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Service Manual
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Device
TV / LCD / MAJOR ICs INFORMATION
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lc-37p55e-sm12.pdf
Date

Sharp LC-37P55E (serv.man12) Service Manual ▷ View online

45
 LC-26GA5E
 LC-32GA5E
  LC-26P55E
  LC-32P55E
  LC-37P55E
Very low power consumption at micro-loads (burst mode).
Start-up circuit eliminates the need for start-up resistor.
Excess current protection (ON period limitation, primary current limitation), excess voltage protection, and thermal 
shut-down function are incorporated.
FD607WJ (RC/LED UNIT):
·
 IC101 :  OPC
   Part number:  
TPS850
  Sharp code:  
VHITPS850++-1Y
The TPS850 is a linear-output photo-IC which incorporates a photodiode and current amp circuit in a single chip. This 
photo-IC is current output type, so can set up output voltage freely by arbitrary load resistance.
FD608WJ (TUNER UNIT):
· IC201 :  IF-Demodulator/PLL
   Part number:  
TDA9886
   Sharp code:  
VHITDA9886+-1Y
The  TDA9886  is  an  alignment-free  multi-standard  (PAL,  SECAM  and  NTSC)  vision  and  sound  IF  signal  PLL
demodulator for positive and negative modulation including sound AM and FM processing.
This IC features the following.
* Gain controlled wide-band vision intermediate frequency (VIF) amplifier (AC-coupled).
*  Multi-standard  true  synchronous  demodulation  with  active  carrier  regeneration  (very  linear  demodulation,
good intermodulation figures reduced harmonics, excellent pulse response).
* Gate phase detector for L/L accent standard.
*  Fully  integrated  VIF  Voltage  Controlled  Oscillator  (VCO),  alignment-free;  frequencies  switchable  for  all
negative modulated standards via I2C bus.
*  4MHz  reference  frequency  input  [signal  from  phase-locked  loop  (PLL)  tuning  system]  or  operating  as  crystal
oscillator.
*  VIF  Automatic  Gain  Control  (AGC)  detector  for  gain  control  operating  as  a  peak  sync  detector  for  negative
modulated signals and as a peak white detector for positive modulated signals.
46
 LC-26GA5E
 LC-32GA5E
  LC-26P55E
  LC-32P55E
  LC-37P55E
2. Detailed ICs Information
SiI 9021      
  
 
 
SiI-DS-0117 
 
 
Pin Diagram 










































144-Pin
TQFP



























































































SiI 9021

















































































































(Top View)


















































 
Figure 1. Pin Diagram 
         
2.1. IC1905  (VHISII9021+-1Q)
2.1.1. Pinning 
2.1.2. Block Diagram
SiI 9021      
  
 
 
SiI-DS-0117 
 
 
SiliconImage Confidential 
For
Sharp 
Internal use Only 
Functional Description 
 SiI 9021                
              SiI 9021                   
                  
       





 
 














PanelLink
TMDS




























PanelLink
TMDS













 






 
 




 
 











 





 






Figure 3. Functional Block Diagram 
 
 SiI 9021                  
The SiI 9021 supports two HDMI input ports. Only one port may be active at any time.
47
 LC-26GA5E
 LC-32GA5E
  LC-26P55E
  LC-32P55E
  LC-37P55E
2.2. IC3002 (RH-IXB624WJZZQ)
2.2.1. Pin Connections and Short Description
 
ADVANCE INFORMATION
VCT 69xyP
Volume 1: General Description
Micronas
November 3, 2004; 6251-644-1-1
AI
1-55
3.12.Pin Connections and Short Description
NC = not connected
LV = if not used, leave vacant
OBL = obligatory; connect as described in circuit 
diagram
IN = Input Pin 
ANA = Analog Pin
OUT = Output Pin
SUPPLY = Supply Pin
VCTP Pin No.
Pin Name
Type
Connection
Short Description
PLQFP
208-1
(If not used)
1
656O6 
P4_6
TDOFW
IN/OUT
LV
Digital 656 Bit 6 Output 
Port 4, Bit 6 Input/Output
JTAG Interface Data Output (firmw. Controler)
2
656O5 
P4_5
TDIFW
IN/OUT
LV
Digital 656 Bit 5 Output 
Port 4, Bit 5 Input/Output
JTAG Interface Data Input (firmw. Controler)
3
656O4 
P4_4
TMSFW
IN/OUT
LV
Digital 656 Bit 4 Output 
Port 4, Bit 4 Input/Output
JTAG Interface Mode Select Input (fw. Contr.)
4
656O3 
P4_3
TCLK
IN/OUT
LV
Digital 656 Bit 3 Output 
Port 4, Bit 3 Input/Output
JTAG Interface Clock Input (TV Controler)
5
656O2 
P4_2
TDO
IN/OUT
LV
Digital 656 Bit 2 Output 
Port 4, Bit 2 Input/Output
JTAG Interface Data Output (TV Controler)
6
656O1 
P4_1
TDI
IN/OUT
LV
Digital 656 Bit 1 Output 
Port 4, Bit 1 Input/Output
JTAG Interface Data Input (TV Controler)
7
656O0 
P4_0
TMS
IN/OUT
LV
Digital 656 Bit 0 Output (LSB)
Port 4, Bit 0 Input/Output
JTAG Interface Mode Select Input (TV Contr.)
8
RESETQ
IN/OUT
OBL
Reset Input/Output
9
AIN1R
IN
GND
Analog Audio 1 Input, Right
10
AIN1L
IN
GND
Analog Audio 1 Input, Left
11
AIN2R
IN
GND
Analog Audio 2 Input, Right
12
AIN2L
IN
GND
Analog Audio 2 Input, Left
13
AIN3R
IN
GND
Analog Audio 3 Input, Right
14
AIN3L
IN
GND
Analog Audio 3 Input, Left
15
AIN4R
IN
GND
Analog Audio 4 Input, Right
16
AIN4L
IN
GND
Analog Audio 4 Input, Left
17
VREFAU
ANA
OBL
Reference Voltage, Audio
18
VSUP8.0AU
SUPPLY
OBL
Supply Voltage Analog Audio, 8.0 V
19
GNDA
SUPPLY
OBL
Ground Analog Audio, Platform Ground
20
SGND
ANA
OBL
Analog Signal GND
48
 LC-26GA5E
 LC-32GA5E
  LC-26P55E
  LC-32P55E
  LC-37P55E
VCT 69xyP
ADVANCE INFORMATION
Volume 1: General Description
1-56
November 3, 2004; 6251-644-1-1
AI
Micronas
21
AOUT2R
AIN5R
IN/OUT
LV
Analog Audio 2 Output, Right
Analog Audio 5 Input, Right
22
AOUT2L
AIN5L
IN/OUT
LV
Analog Audio 2 Output, Left
Analog Audio 5 Input, Left
23
AOUT1R
OUT
LV
Analog Audio 1 Output, Right
24
AOUT1L
OUT
LV
Analog Audio 1 Output, Left
25
HEADPHONER
OUT
LV
Analog Headphone Output, Right
26
HEADPHONEL
OUT
LV
Analog Headphone Output, Left
27
SPEAKERR
OUT
LV
Analog Loudspeaker Output, Right
28
SPEAKERL
OUT
LV
Analog Loudspeaker Output, Left
29
SUBWOOFER 
TEST
IN/OUT
LV
Analog SUBWOOFER Output 
Test Input
30
VREFSIF
ANA
OBL
Reference Voltage, Audio SIF
31
SIFIN+
IN
VREF
IF
Differential IF Input
32
SIFIN-
IN
VREF
IF
Differential IF Input
33
VSUP5.0SIF
SUPPLY
OBL
Supply Voltage Analog SIF, 5.0 V
34
GNDA
SUPPLY
OBL
Ground Analog SIF, Platform Ground
35
GND3.3DIG
SUPPLY
OBL
Ground Digital Audio Core
36
VSUP3.3DIG
SUPPLY
OBL
Supply Voltage Digital Audio Core, 3.3 V
37
SPDIF_OUT
OUT
LV
SPDIF Output
38
I2S_DA_IN
IN
LV
Audio Bus Data Input
39
I2S_CL
IN
LV
Audio Bus Clock Input
40
I2S_WS
IN
LV
Audio Bus Word Strobe Input
41
I2S_DEL_OUT
OUT
LV
Audio Delay Line Bus Data Output
42
I2S_DEL_IN
IN
LV
Audio Delay Line Bus Data Input
43
I2S_DEL_CL
OUT
LV
Audio Delay Line Bus Clock Output
44
I2S_DEL_WS
OUT
LV
Audio Delay Line Bus Word Strobe Output
45
VSUP3.3RAM
SUPPLY
OBL
Supply Voltage Ram, 3.3 V
46
GND3.3RAM
SUPPLY
OBL
Ground Ram
47
DVS
IN
LV
Digital or Analog Video VSYNC HD Input
48
DEN
IN
LV
Digital Video Enable Input 
49
DCLK
IN
LV
Digital Video Clock Input 
50
DRI7
IN
LV
Digital Video Red 7 Input 
VCTP Pin No.
Pin Name
Type
Connection
Short Description
PLQFP
208-1
(If not used)
2.2.1. Pin Connections and Short Description
  
(Continued)
Page of 24
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  • Here you can View online or download the Service Manual for the Sharp LC-37P55E (serv.man12) in PDF for free, which will help you to disassemble, recover, fix and repair Sharp LC-37P55E (serv.man12) LCD. Information contained in Sharp LC-37P55E (serv.man12) Service Manual (repair manual) includes:
  • Disassembly, troubleshooting, maintenance, adjustment, installation and setup instructions.
  • Schematics, Circuit, Wiring and Block diagrams.
  • Printed wiring boards (PWB) and printed circuit boards (PCB).
  • Exploded View and Parts List.