Sharp LC-37P55E (serv.man12) Service Manual ▷ View online
58
LC-26GA5E
LC-32GA5E
LC-26P55E
LC-32P55E
LC-37P55E
VCT 69xyP
ADVANCE INFORMATION
Volume 1: General Description
1-66
November 3, 2004; 6251-644-1-1
AI
Micronas
SUBWOOFER – Subwoofer Outputs
Output of the subwoofer signal
I2S_DEL_WS - Delay Line Bus Word Strobe
This is the word strobe signal of the delay line bus.
I2S_DEL_CL - Delay Line Bus Clock
This is the Clock signal of the delay line bus.
I2S_DEL_IN - Delay Line Bus Data Input
This is the data input signal of the delay line bus.
I2S_DEL_OUT - Delay Line Bus Data Output
This is the data output signal of the delay line bus.
I2S_WS - I2S Word Strobe
This is the word strobe signal of I2S bus.
I2S_DA_IN - I2S Data Input
This is the data input signal of I2S bus.
I2S_CL - I2S Clock
This is the Clock signal of I2S bus.
SPDIF_OUT -
This is an SPDIF output signal to connect to an A/V
receiver.
SIF
−/+ − Sound IF Input
This is the SIF input to connect to an external DRX.
VREFSIF – Reference Voltage for SIF
This pin serves as the internal ground connection for
the analog audio circuitry.
3.13.3.Video Pins
656I 0-7
− Digital 656 Data Input
These are the 8 bits digital 656 video inputs.
656CLKI
− Digital 656 Input clock
This is the clock for the digital 656 video inputs.
656O 0-7
− Digital 656 Data Output
These are the 8 bits digital 656 video outputs.
656CLKO
− Digital 656 output clock
This is the clock for the digital 656 video outputs.
OSDR 0-3
− Graphic Data input/output
These are the 2 or 4 bit graphic input/output
OSDG 0-3
− Graphic Data input/output
These are the 2 or 4 bit graphic input/output
OSDB 0-3
− Graphic Data input/output
These are the 2 or 4 bit graphic input/output
OSDHCS 0-1
− Graphic Half Contrast Input/Output
This is the half contrast for the graphic input/output
OSDFSW
− Graphic Fast Switch Input/Output
This is the fast switch for the graphic input/output
OSDCLK
− Graphic clock Input/Output
This is the clock for the graphic video input/output
OSDV
− Graphic vertical sync Input/Output
This is the vertical sync for the graphic input/output
OSDH
− Graphic horizontal sync Input/Output
This is the horizontal sync signal for the graphic I/O
DRO1_ 0-9 - Digital Red Outputs
This are 10 bits digital signals for red outputs,
for dual RGB use bits (0-7).
DGO1_ 0-9 - Digital Green Output
This are 10 bits digital signals for green outputs,
for dual RGB use bits (0-7).
DBO1_ 0-9 - Digital Blue Outputs
This are 10 bits digital signals for blue outputs,
for dual RGB use bits (0-7).
DRO2_ 0-7 - Digital dual Red Outputs
This are 8 bits digital signals for red outputs.
DGO2_ 0-7 - Digital dual Green Output
This are 8 bits digital signals for green outputs.
DBO2_ 0-7 - Digital dual Blue Outputs
This are 8 bits digital signals for blue outputs.
PCS 0-5 - LCD Panel Control Select Outputs
This are 6 control select signals for LCD outputs.
For CRT application use PCS_0 as H sync and PCS_1
as V sync Back End.
PCLK1,2 - LCD Panel Clock Outputs
This are the clock signals for LCD/RGB outputs.
LVDSA_* - LCD Panel LVDS Outputs
This are 12 signals and clocks for LVDS single or dual
output.
LVDSB_* - LCD Panel LVDS Outputs
This are 10 signals and clocks for LVDS dual output.
REXT - LVDS External Resistor
This pin is connected to the external LVDS resistor.
(6.2 kOhm to gnd)
DRI 0-7 - Digital video inputs for Red
This are 8 bits digital inputs for red signal
DGI 0-7- Digital video inputs for Green
This are 8 bits digital inputs for green signal
DBI 0-7- Digital video inputs for Blue
This are 8 bits digital inputs for blue signal.
2.2.2.3 Video Pins
2.2.2. Pin Descriptions (Continued)
59
LC-26GA5E
LC-32GA5E
LC-26P55E
LC-32P55E
LC-37P55E
ADVANCE INFORMATION
VCT 69xyP
Volume 1: General Description
Micronas
November 3, 2004; 6251-644-1-1
AI
1-67
DEN - Digital video inputs Enable
This is the enable signal for the Digital Video Inputs.
DHS - Digital video inputs Horizontal Sync
This is the H Sync signal for the Digital RGB input bus
or for the VGA Video Inputs.
DVS - Digital video inputs Vertical Sync
This is the V Sync signal for the Digital RGB input bus
or for the VGA Video Inputs.
DCLK - Digital video inputs Clock
This is the Clock signal for the Digital Video Inputs.
CLKOUT
− Digital Output clock
This is a 20MHz clock for the external video ICs.
VIN 1–22
− Analog Video Input
These are the 19 analog video inputs.
(Vin 4,10 and 14 are missing)
A CVBS, S-VHS, YCrCb or RGB signal is converted
using the luma, chroma and component AD converter.
Vin 8,18 are fast blank inputs. Vin22 is an Hsync input.
The input signals must be AC-coupled.
VOUT 1-3
− Analog Video Output
The analog video inputs that are selected by the video
matrix are output at these pins.
ROUT, GOUT, BOUT
− Analog RGB Output
These pins are the analog Red/Green/Blue outputs of
the back-end.
SVMOUT
− Scan Velocity Modulation Output
This output delivers the analog SVM signal. The D/A
converter is a current sink like the RGB D/A convert-
ers. At zero signal the output current is 50% of the
maximum output current.
3.13.4.Controller Pins
XTALIN Crystal Input and XTALOUT Crystal Output
These pins are connected to an 20.25 MHz crystal
oscillator. An external clock can be fed into XTALIN.
RESETQ
− Reset Input/Output
A low level on this pin resets the VCT 69xyP. The
internal CPU can pull down this pin to reset external
devices connected to this pin.
TEST
− Test Input
This pin enables factory test modes. For normal opera-
tion, it must be connected to ground.
SCL
− I
2
C Bus Clock
This pin delivers the I
2
C bus clock line. The signal can
be pulled down by external slave ICs to slow down
data transfer.
SDA
− I
2
C Bus Data
This pin delivers the I
2
C bus data line.
P1_0
−P1_3 − I/O Port
These pins provide CPU controlled I/O ports.
P1_4
−P1_7 − I/O Port
These pins provide CPU controlled I/O ports.
Also used as CADC1
−4 − Controller A/D inputs 1 to 4.
This 4 pins are analog/digital converters from the con-
troller
P2_0
−P2_7 − I/O Port
These pins provide CPU controlled I/O ports.
P3_0
−P3_7 − I/O Port
These pins provide CPU controlled I/O ports.
P4_0
−P4_7 − I/O Port
These pins provide CPU controlled I/O ports.
TDO-TCLK-TDI-TMS -JTAG Interface Pins for TV con-
troler.
TCLK at pin 4 (656O3) has during reset an internal pull
up: (TCLK=0) at end of reset enables the JTAG mode
at 656 LSB’s, this can also be done via I2C.
This JTAG is also available at Port(1 and 2) but only
via I2C.
TDOFW-TCLKFW-TDIFW-TMSFW -JTAG Interface
Pins for firmware controler.
TCLKFW at pin 208 (656O7) has during reset an inter-
nal pull up: (TCLKFW=0) at end of reset enables the
JTAG mode, this can also be done via I2C.
2.2.2.4 Controller Pins
60
LC-26GA5E
LC-32GA5E
LC-26P55E
LC-32P55E
LC-37P55E
VCT 69xyP
ADVANCE INFORMATION
Volume 1: General Description
1-68
November 3, 2004; 6251-644-1-1
AI
Micronas
Table 3–10: Maximum Number of Ports
Display
CRT
FPD
Application
Analog RGB + SVMOUT + H + V
TTL (Single RGB),
LVDS (Dual or Single)
TTL (Dual RGB)
Panel
control
X
X
X
X
X
X
X
X
X
X
X
X
656IN
X
X
X
X
X
X
X
X
X
X
X
X
656OUT
X
X
X
X
X
X
X
X
X
X
OSD444
X
X
X
X
X
X
X
X
OSD222
X
X
X
X
Port 1
4
4
4
4
4
4
4
4
8
8
8
8
8
8
8
8
8
8
8
8
Port 2
8
8
8
8
8
8
8
8
6
6
6
6
6
6
6
6
6
6
6
6
Port 3
6
8
8
6
8
8
6
6
8
6
8
8
8
8
Port 4
2
2
2
2
8
8
8
8
8
8
8
8
8
8
Max Number
of Ports
14
20
22
22
20
26
28
28
14
20
20
22
22
28
30
30
14
22
22
30
Note: 24bit RGB input is always available
Maximum Number of Ports
61
LC-26GA5E
LC-32GA5E
LC-26P55E
LC-32P55E
LC-37P55E
VCT 69xyP
ADVANCE INFORMATION
Volume 1: General Description
1-70
November 3, 2004; 6251-644-1-1
AI
Micronas
VCT 69xyP
LVDS output
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
15
4
15
3
15
2
15
1
15
0
14
9
14
8
14
7
14
6
14
5
14
5
14
4
14
3
14
2
14
1
14
0
13
9
13
8
13
7
13
6
13
5
13
4
13
3
13
2
13
1
13
0
12
9
12
8
12
7
12
6
12
5
12
4
12
3
12
2
12
1
12
0
11
9
11
8
11
7
11
6
11
5
11
4
11
3
11
2
11
1
11
0
10
9
10
8
10
7
10
6
10
5
15
6
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
58
57
56
55
55
54
53
65
6O
6
65
6O
5
65
6O
4
65
6O
3
65
6O
2
65
6O
1
65
6O
0
R
E
S
E
T
Q
A
IN
1R
A
IN
1L
A
IN
2R
A
IN
2L
A
IN
3R
A
IN
3L
A
IN
4R
A
IN
4L
V
R
E
F
A
U
V
S
U
P
8.
O
A
U
A
O
U
T
2R
A
O
U
T
2L
A
O
U
T
1R
S
G
N
D
G
N
D
A
A
O
U
T
1L
H
E
A
D
P
H
O
N
E
R
H
E
A
D
P
H
O
N
E
L
S
P
E
A
K
E
R
R
S
U
B
W
O
O
F
E
R
V
R
E
F
S
IF
S
IF
IN
+
S
IF
IN
-
S
P
E
A
K
E
R
L
V
S
U
P
5.
0S
IF
G
N
D
A
G
N
D
3.
3D
IG
V
S
U
P
3.
3D
IG
S
P
D
IF
_O
U
T
I2
S
_D
A
_I
N
I2
S
_D
E
L
_O
U
T
I2
S
_D
E
L
_I
N
I2
S
_D
E
L
_C
L
I2
S
_W
S
I2
S
_C
L
I2
S
_D
E
L
_W
S
V
S
U
P
3.
3R
A
M
G
N
D
3.
3R
A
M
D
V
S
D
C
L
K
D
R
I7
D
R
I6
D
R
I5
D
E
N
V
S
U
P
1.
8D
IG
G
N
D
1.
8D
IG
V
S
U
P
3.
3L
V
D
S
L
V
D
S
A
_4
P
P
C
L
K
1
P
C
L
K
2
P
C
S
0
P
C
S
1
P
C
S
4
P
C
S
5
V
S
U
P
3.
3I
O
1
P
C
S
3
P
C
S
2
G
N
D
3.
3I
O
1
O
S
D
R
0
O
S
D
R
1
O
S
D
R
2
O
S
D
G
0
O
S
D
G
1
O
S
D
G
2
O
S
D
G
3
O
S
D
R
3
L
V
D
S
A
_4
N
G
N
D
3.
3L
V
D
S
L
V
D
S
A
_3
P
L
V
D
S
A
_3
N
V
S
U
P
3.
3L
V
D
S
L
V
D
S
A
_C
L
K
P
L
V
D
S
A
_C
L
K
N
G
N
D
3.
3L
V
D
S
L
V
D
S
A
_2
P
L
V
D
S
A
_2
N
V
S
U
P
3.
3L
V
D
S
L
V
D
S
A
_1
P
L
V
D
S
A
_1
N
V
S
U
P
1.
8L
V
D
S
L
V
D
S
A
_0
P
L
V
D
S
A
_0
N
G
N
D
1.
8L
V
D
S
R
E
X
T
L
V
D
S
B
_3
P
G
N
D
3.
3L
V
D
S
L
V
D
S
B
_3
N
V
S
U
P
3.
3L
V
D
S
L
V
D
S
B
_C
L
K
P
L
V
D
S
B
_C
L
K
N
G
N
D
3.
3L
V
D
S
L
V
D
S
B
_2
P
L
V
D
S
B
_2
N
V
S
U
P
3.
3L
V
D
S
L
V
D
S
B
_1
P
L
V
D
S
B
_1
N
VIN16
VIN15
VIN13
VIN12
VIN11
VIN9
VIN8
VIN6
VIN5
VIN3
VIN2
VIN7
VIN1
VIN22
VIN21
VIN20
VIN19
VIN17
VIN18
GNDA
VSUP1.8FE
VSUP3.3VO
VOUT3
VOUT2
VSUP3.3IO3
656I0
656I1
GND3.3IO3
VOUT1
656I2
656I3
656I4
656I5
656I7
656CLKI
656CLKO
656O7
656I6
P1_7
P1_6
P1_5
P1_4
GND3.3DAC
VSUP3.3DAC
P1_3
P1_2
P1_1
P1_0
VSUP1.8FE
VSUP3.3FE
LVDSB_0P
LVDSB_0N
CLKOUT
SDA
SCL
XTALOUT
XTALIN
HSO
VSO
GND3.3COM
VSUP3.3DRI
GND3.3DRI
DBI0
VSUP3.3COM
DBI1
OSDB0
OSDB1
OSDB2
OSDB3
OSDHCS0
OSDHCS1
OSDFSW
OSDCLK
VSUP3.3IO1
GND3.3IO1
OSDH
OSDV
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
GND3.3FL
VSUP3.3FL
DBI2
DBI3
DBI4
DBI5
DBI6
DGI1
DGI2
DGI3
DGI0
DBI7
DGI4
DGI5
DGI6
DGI7
DRI1
DRI2
DRI3
DRI4
DRI0
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
197
198
199
200
200
201
202
203
204
205
206
206
207
208
2.2.3. Pinning
Important Note from MICRONAS:
All information and data contained in the data sheet are without any commitment, are not to be considered as an offer
for conclusion of a contract, not shall they be construed as to create any liability. Any new issue of this data sheet in-
validates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples delivered.
By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third par-
ties which may result from its use.
Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time,
without obligation to notify any person or entity of such revisions or changes.
Click on the first or last page to see other LC-37P55E (serv.man12) service manuals if exist.