Sharp LC-37AD5E (serv.man5) Service Manual ▷ View online
LC-37AD5E
5 – 13
2.7. ICIC1710 (RH-IXB823WJZZQ)
2.7.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
Sheet Name
1
EXP [7]
O
Outport [7] (I2C SEL signal)
DTI2CSEL
2
EXP [6]
O
Outport [6] (Digital circuit reset signal)
DTM_RESET
3
EXP [5]
O
Outport [5] (Digital circuit power control signal)
DTV_ON
4
GND*
–
Ground
N.C.
5
EXP [3]
O
Outport [3] (Inverter ON control signal)
BL_ON
6
GND*
–
Ground
N.C.
7
OFLOUT
O
OFL signal output
OFLOUT
8
OSCOUT
O
OSC signal output
OSCOUT
9
VCCIO1
–
VCC (3.3V)
FPGA_VCC
10
GNDIO
–
Ground
Ground.
11
GNDINT
–
ground.
Ground.
12
PCLK
I
Reference clock input
PCLK
13
VCCINT
–
VCC (3.3V)
FPGA_VCC
14
GCLR
I
RESET terminal. L: RESET, H: Normal
RESET_N
15
GND*
–
N.C.
N.C.
16
GND*
–
N.C.
N.C.
17
GND*
–
N.C.
N.C.
18
GND*
–
N.C.
N.C.
19
GND*
–
N.C.
N.C.
20
GND*
–
N.C.
N.C.
21
GND*
–
N.C.
N.C.
22
#TMS
I
Pin for JTAG write (Test Mode Select)
FPGA_TMS
23
#TDI
I
Pin for JTAG write (Test Data Input)
FPGA_TDI
24
#TCK
I
Pin for JTAG write (Test Clock)
FPGA_TCK
25
#TDO
O
Pin for JTAG write (Test Data Input)
FPGA_TDO
26
VSYNC
I
V sync input (not used)
V_SYNC
27
HSYNC
I
H sync input (not used)
H_SYNC
28
GND*
–
N.C.
N.C.
29
GND*
–
N.C
N.C.
30
DMY_IN
I
Dummy pin for RESET line wiring (no effect on operation)
RESET_N
31
VCCIO1
–
VCC (3.3V)
FPGA_VCC
32
GNDIO
–
Ground.
Ground.
33
GND*
–
N.C.
N.C.
34
GND*
–
N.C.
N.C.
35
SCK
I
Microprocessor control bus clock
SCK
36
GND*
–
N.C.
N.C.
37
GND*
–
N.C.
N.C.
38
GND*
–
N.C.
N.C.
39
GND*
–
N.C.
N.C.
40
GND*
–
N.C.
N.C.
41
SEN
I
Microprocessor control bus enable
SDE
42
SDA
I
Microprocessor control bus data
SDA
43
GND*
–
N.C.
N.C.
44
GND*
–
N.C.
N.C.
45
VCCIO1
–
VCC (3.3V)
FPGA_VCC
46
GNDIO
–
Ground.
Ground.
47
GND*
–
N.C.
N.C.
48
GND*
–
N.C.
N.C
49
GND*
–
N.C.
N.C.
50
GND*
–
N.C.
N.C.
51
GND*
–
N.C.
N.C.
52
GND*
–
N.C.
N.C.
53
GND*
–
N.C.
N.C.
54
GND*
–
N.C.
N.C.
55
GND*
–
N.C.
N.C.
56
GND*
–
N.C.
N.C.
57
GND*
–
N.C.
N.C.
58
GND*
–
N.C.
N.C.
59
VCCIO2
–
VCC (3.3V)
FPGA_VCC
60
GNDIO
–
Ground.
Ground.
61
GND*
–
Ground.
N.C.
LC-37AD5E
5 – 14
62
GND*
–
Ground.
Ground.
63
VCCINT
–
VCC (3.3V)
FPGA_VCC
64
GND*
–
Ground.
Ground.
65
GNDINT
–
Ground.
Ground.
66
GND*
–
N.C.
N.C.
67
GND*
–
N.C
N.C.
68
GND*
–
N.C
N.C.
69
GND*
–
N.C
N.C.
70
GND*
–
N.C
N.C.
71
GND*
–
N.C
N.C.
72
GND*
–
N.C
N.C.
73
GND*
–
N.C
N.C.
74
GND*
–
N.C
N.C.
75
GND*
–
N.C
N.C.
76
EXP [1]
O
Outport [1] (Power control signal ANT5V)
EP1
77
GND*
–
N.C
N.C.
78
GND*
–
N.C.
N.C.
79
GNDIO
–
Ground.
Ground.
80
VCCIO2
–
VCC (3.3V)
FPGA_VCC
81
GND*
–
N.C.
N.C
82
GND*
–
N.C.
N.C
83
GND*
–
N.C.
N.C
84
GND*
–
N.C.
N.C
85
GND*
–
N.C.
N.C
86
GND*
–
N.C.
N.C
87
GND*
–
N.C.
N.C
88
GND*
–
N.C.
N.C
89
GND*
–
N.C.
N.C
90
GND*
–
N.C.
N.C
91
EXP [4]
O
Outport [4] (Power control signal 2)
PCON2 (EP4)
92
GND*
–
N.C.
N.C
93
GNDIO
–
Ground.
Ground.
94
VCCIO2
–
VCC (3.3V)
FPGA_VCC
95
GND*
–
N.C.
N.C
96
GND*
–
N.C.
N.C
97
EXP [2]
O
Outport [2] (Power control signal 1)
PCON1 (EP2)
98
GND*
–
N.C
N.C
99
GND*
–
N.C.
N.C
100
EXP [0]
O
Outport [0] (S-MUTE signal)
S_MUTE
Pin No.
Pin Name
I/O
Pin Function
Sheet Name
LC-37AD5E
5 – 15
2.8. IC4001 (RH-iXB680WJZZQ)
2.8.1 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
Digital power-supply ball assignment
A8, B8, B19, B20, C8,
D8, F1, F2, F3, F4, U23,
U24, V1, V2, V3, V4,
AA23, AA24, AA25,
AA26, AC7, AC15, AD7,
AD15, AE7, AE15, AF7,
AF15
A8, B8, B19, B20, C8,
D8, F1, F2, F3, F4, U23,
U24, V1, V2, V3, V4,
AA23, AA24, AA25,
AA26, AC7, AC15, AD7,
AD15, AE7, AE15, AF7,
AF15
VDD
—
1.6 V power supply.
B22, C3, C4, C10, D3,
D4, D10, E4, G25, M1,
M2, M3, M4, W23, W24,
AC3, AC4, AC10, AC13,
AC19, AC23, AC24, AD3,
AD4, AD10, AD13, AD19,
AD23, AD24
D4, D10, E4, G25, M1,
M2, M3, M4, W23, W24,
AC3, AC4, AC10, AC13,
AC19, AC23, AC24, AD3,
AD4, AD10, AD13, AD19,
AD23, AD24
VDD3
—
3.3 V power supply.
AD6
RTCVDD
—
Low power controller 1.8 V power supply.
B13, B21, D25, K10 to
K17, L10, L11, L12, L13,
L14, L15, L16, L17, M10,
M11, M12, M13, M14,
M15, M16, M17, N10,
N11, N12, N13, N14,
N15, N16, N17, P10, P11,
P12, P13, P14, P15, P16,
P17, R10 to R17, T10,
T11, T12, T23, T14, T15,
T16, T17, U10, U11, U12,
U13, U14, U15, U16, U17
K17, L10, L11, L12, L13,
L14, L15, L16, L17, M10,
M11, M12, M13, M14,
M15, M16, M17, N10,
N11, N12, N13, N14,
N15, N16, N17, P10, P11,
P12, P13, P14, P15, P16,
P17, R10 to R17, T10,
T11, T12, T23, T14, T15,
T16, T17, U10, U11, U12,
U13, U14, U15, U16, U17
GND
—
Ground for power supplies.
Analog power-supply ball assignment
AE11
AE11
VDDVDACRGB
—
3.3 V power supply for RGB video DAC
AE9
VDDVDACYCC
—
3.3 V power supply for YCC video DAC
AD11
GNDVDACRGB
—
Ground for RGB video DAC
AD9
GNDVDACYCC
—
Ground for YCC video DAC
AD8
SHIELDVDAC
—
Shield ground for 2 x video DACs
AE10
IREFDACRGB
—
RGB video DAC current reference
AE8
IREFDACYCC
—
YCC video DAC current reference
AC9
VREFDACRGB
—
RGB video DAC voltage reference
AC8
VREFDACYCC
—
YCC video DAC voltage reference
A10
VDDVPLL
—
Supply 3.3 V power for video PLL
C13
VDDAUDIOFSYN
—
Supply 1.8 V dedicated power for low jitter audio clock frequency synthe-
sizer
sizer
B12
GNDAUDIOFSYN
—
Dedicated ground for low jitter audio clock frequency synthesizer
C12
VDDGENFSYN
—
1.8 V dedicated power for non audio clock frequency synthesizer
B11
GNDGENFSYN
—
Dedicated ground for non audio clock frequency synthesizer
AA4
VDDAADAC
—
3.3 V power for audio DAC
AA2
VSSAADAC
—
Ground for audio DAC command switches
Y4
VDDASADAC
—
3.3 V power for audio DAC substrate
AB2
VCCAADAC
—
3.3 V power for audio DAC command switches
AB3
GNDAADAC
—
Ground for audio DAC
AC2
VCCASADAC
—
3.3 V power for audio DAC command switches substrate
AD2
IREF
—
Audio DAC output reference current
AE2
VBGFIL
—
Audio DAC filtered output reference voltage
RTC ball assignment
AF4
AF4
LPCLKIN
I
Low power clock input (1.8V tolerant).
AF5
LPCLKOSC
O
Low power clock oscillator (1.8V tolerant).
A16
NO32XTAL
I
Select for 32kHz clock source. 0:XTAL 1:Internel divider
System ball assignment
A13
A13
CLK27MA
I
Selectable input clock to PLL or for x1 mode (5 V tolerant)
A11
CLKSPEEDSEL
I
PLL speed select (5 V tolerant)
A12
AUXCLKOUT
O
Auxiliary clock for general use (5 V tolerant)
AF6
not RESET
I
System reset (1.8 V tolerant)
AD14
not WDOGRSTOUT
O
Internal watchdog timer reset (5 V tolerant)
LC-37AD5E
5 – 16
Pin No.
Pin Name
I/O
Pin Function
JTAG ball assignment
AE14
AE14
TDI
I
Boundary scan test data input (5 V tolerant)
AC14
TMS
I
Boundary scan test mode select (5 V tolerant)
AF16
TCK
I
Boundary scan test clock (5 V tolerant)
AF14
not TRST
I
Boundary scan test logic reset (5 V tolerant)
AE13
TDO
O
Boundary scan test data output (5 V tolerant)
DCU ball assignment
P1
P1
DCUTRIGGERIN
I
External trigger input to DCU (5 V tolerant)
P3
DCUTRIGGEROUT
O
Signal to trigger external debug circuitry (5 V tolerant)
Transport stream 2 ball assignment
C23
C23
TSIN2LBYTECLK
I/O
Transport stream bit clock (5 V tolerant)
C22
TSIN2LBYTECLKVALID
I/O
Transport stream bit clock valid edge (5 V tolerant)
B23
TSIN2LERROR
I/O
Transport stream packet error (5 V tolerant)
D19
TSIN2LPACKETCLK
I/O
Transport stream packet strobe (5 V tolerant)
B18, C18, D18, C19,
C20, D20, C21, D21
C20, D20, C21, D21
TSIN2LDATA[7:0]
I/O
Transport stream data (5 V tolerant)
(TSIN2LDATA7 is used for data input in serial mode)
(TSIN2LDATA7 is used for data input in serial mode)
Transport stream 1 ball assignment
P23
P23
TSIN1BYTECLK
I
Transport stream bit/byte clock (5 V tolerant)
M24
TSIN1BYTECLKVALID
I
Transport stream bit/byte clock valid edge (5 V tolerant)
M26
TSIN1ERROR
I
Transport stream packet error (5 V tolerant)
N26
TSIN1PACKETCLK
I
Transport stream packet strobe (5 V tolerant)
K26, J25, H24, J24, L26,
L25, L24, M23.
L25, L24, M23.
TSIN1DATA[7:0]
I
Transport stream data in (5 V tolerant)
(TSIN1DATA7 is used for data input in serial mode)
(TSIN1DATA7 is used for data input in serial mode)
EMI ball assignment
L3
L3
not EMIRAS or not CI_IORD
O
Row address strobe for SDRAM
K1
not EMICAS or not CI_IOW
O
Column address strobe for SDRAM
J1
not EMICSA
O
Peripheral chip select A
K3
not EMICSB
O
Peripheral chip select B
K2
not EMICSC
O
Peripheral chip select C
N4
not EMICSD
O
Peripheral chip select D
J2
not EMICSE
O
Peripheral chip select E
L2
not EMICSF
O
Peripheral chip select F
L1, N3
not EMIBE[1:0]
O
External device data bus byte enable. 1 bit per byte of the data bus.
N1
not EMIOE or not CI_OE
O
External device output enable.
N2
not EMILBA or not CI_Wea
O
Flash device load burst address.
P4
EMIWAIT not TREADY
I
External memory device target ready indicator (5 V tolerant)
P2
EMIRD not WR
O
External read/write access indicator. Common to all devices.
H3, H2, G2, H4, G4, E2,
E1, E3, H1, D1, D2, C2,
G3, C1, B1, A1.
E1, E3, H1, D1, D2, C2,
G3, C1, B1, A1.
EMIDATA[15:0]
I/O
External common data bus.
D5, C5, D6, B3, A2, B2,
A3, B4, A4, C6, B5, A5,
D7, C7, B6, A6, B7, A7,
D9, C9, B9, A9, B10, C11
A3, B4, A4, C6, B5, A5,
D7, C7, B6, A6, B7, A7,
D9, C9, B9, A9, B10, C11
EMIADDR[25:2]
O
External common address bus
J3
not EMIREQGNT
O
Bus request/grant indicator
K4
not EMIACKREQ
I
Bus grant/request indicator (5 V tolerant)
L4
EMIBOOTMODE0
I
External power-up port size indicator (5 V tolerant)
G1
EMISDRAMCLK
O
SDRAM clock
J4
EMIFLASHCLK
O
Peripheral clock
Programmable I/O ball assignment
W1, U4, U2, U1, R2, R1,
T2, T1
W1, U4, U2, U1, R2, R1,
T2, T1
PIO0[7:0]
I/O
Parallel input/output pin or alternative function (5 V tolerant)
AB4, Y2, AA1, Y1, W3,
U3, W2, W4
U3, W2, W4
PIO1[7:0]
I/O
AF3, AD5, AE3, AE5,
AF2, Y3, AA3, AF1
AF2, Y3, AA3, AF1
PIO2[7:0]
I/O
AE18, AE4, AC16, AC12,
AE6, AC11, AC5, AE12
AE6, AC11, AC5, AE12
PIO3[7:0]
I/O
AE20, AD20, AF20,
AE19, AC17, AD18,
AD17, AF19
AE19, AC17, AD18,
AD17, AF19
PIO4[7:0]
I/O
AC22, AF22, AD21,
AC21, AE21, AC18,
AC20, AF21
AC21, AE21, AC18,
AC20, AF21
PIO5[7:0]
I/O
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