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Model
LC-37AD1E (serv.man10)
Pages
18
Size
740.39 KB
Type
PDF
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Service Manual
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Device
TV / LCD / major IC informations
File
lc-37ad1e-sm10.pdf
Date

Sharp LC-37AD1E (serv.man10) Service Manual ▷ View online

59
59-1
59-2
LC-37AD1E
Ë
VHIFA3675F/-1 (ASSY:IC1702)
6-channel DC-DC converter IC
»
Block Diagram
»
Pin Function
Pin No
.
Pin Name
I/O
Pin Function
1
VCC1
Power supply for control circuit.
2R
T
Oscillator timing resistor.
3C
T
Oscillator timing capacitor.
4
CS3
Soft start for Ch.3 & Ch.4.
5
CS5
Soft start for Ch.6.
6
CS4
Soft start for Ch.5.
7
CS1
Soft start for Ch.1
8
CS2
Soft start for Ch.2.
9
VREF
O
Reference voltage output.
10
CREF
O
C
apacitor for reference voltage output.
11
VREG
O
Regulated for voltage  output.
12
IN2-
I
Ch.2 inverting input to error amplifier.
13
FB2
O
Ch.2 output of error amplifier.
14
IN1-
I
Ch.1 inverting input to error amplifier.
15
FB1
O
Ch.1 output of error amplifier.
16
IN5+
I
Ch.5 non-inverting input to error amplifier.
17
IN5-
I
Ch.5 inverting input to error amplifier.
18
FB5
O
Ch.5 output of error amplifier.
19
IN6-
I
Ch.6 inverting input to error amplifier.
20
FB6
O
Ch.6 output of error amplifier.
21
IN3+
I
C
h.3 non-inverting input to error amplifier.
22
IN3-
I
Ch.3 inverting input to error amplifier.
23
FB3
O
Ch.3 output of error amplifier.
24
IN4+
I
C
h.4 non-inverting input to error amplifier.
25
IN4-
I
Ch.4 inverting input to error amplifier.
26
FB4
O
Ch.4 output of error amplifier.
27
CP
I
T
iming capacitor for timer latch delay.
28
GND
Ground.
29
TLSEL
I
Ch.3 & Ch.4 timer latch selection(Low:disable).
30
CNT5
I
Ch.6 ON/OFF function.
31
CNT4
I
C
h.5 ON/OFF function.
32
CNT2
I
Ch.2 ON/OFF function.
33
CNT3
I
Ch.3 & Ch.4 ON/OFF function.
34
CNT1
I
C
h.1 ON/OFF function.
35
VCC2
Power supply for output stage.
36
VDRV
O
Bias for logic circuit of output.
37
PGND1
Power ground.
38
OUT1S
O
Ch.1 source electrode of output stage.
39
OUT1
O
Ch.1 output(for Pch-MOSFET)
40
OUT4
O
Ch.4 output(for Pch-MOSFET)
41
OUT3
O
Ch.3 output(for Pch-MOSFET)
42
OUT2S
O
Ch.2 source electrode of output stage.
43
OUT2
O
Ch.2 output(for Pch-MOSFET)
44
OUT6S
O
Ch.6 source electrode of output stage.
45
OUT6
O
Ch.6 output(for Pch-MOSFET)
46
OUT5
O
Ch.5 output(for Pch-MOSFET)
47
OUT5S
O
Ch.5 source electrode of output stage.
48
PGND2
Power ground.
60
60-1
60-2
LC-37AD1E
Ë
VHIMD1422N+-1Y(ASSY:IC1706)
DC-DC converter power IC
»
Block Diagram
Pin No
.
Pin Name
I/O
Pin Function
1
S/S
I
capacitor connection terminal for a soft start.
2
OCL-
I
Over(
) current-detection terminal.
3
OCL+
I
O
ver-current (+) detection terminal.
4,26
GND
GND terminal.
5
R/C
I
Remote ON/OFF control terminal.
6
Vcc
Power supply terminal of a control circuit.
8
Vboot
I
P
ower supply terminal of a main switch and MOSFET control circuit.
9
VGL
I
Gate terminal of the Low side MOSFET for periodic rectification.
11~14
VOUT
O
Output terminal of the power stage.
16
P.GND
GND terminal of an output circuit.
18~21
VDD
Power supply terminal of the main switch MOSFET.
23
VGH
I
Gate terminal of the high side MOSFET for periodic rectification.
25
VB
I
Output bootstrap terminal.
Capacitor is connected between VB terminal and VOUT and the circuit for
control of MOSFET inside IC is bootstrapped.
27
VTS
Terminal for TEST. Please do not connect anywhere.
28
Vref
I
Internal standard voltage output terminal.
30
ampOUT
O
Built-in error amplifier output terminal.
32
amp-
I
Built-in error amplifier reversal input terminal. .
7,10,15,17,
N/C
It is a no-connection terminal.
22,24,29,31
»
Pin Function
Ë
RH-IXA802WJN1Q(ASSY:IC1901)
PLD(Programmable Logic Device)
»
Pin Function
Pin No
.
P
in Name
I/O
Pin Function
1N
C
Non connection
2
SP_CP2
I
C
lamp signal input terminal from the synchronous separation IC.
(with 15K system)
3
S
P_VD
I
Vertical synchronized signal input terminal from the synchronous separation IC
4
GND
Ground
5
SP_HD
I
Horizontal synchronized signal input terminal from the synchronous separation IC
6
VD3
O
Vertical synchronized signal output terminal to the synchronous separation IC
7
HD3
O
Horizontal synchronized signal output terminal to the synchronous separation IC
8
SP_CP1
I
C
lamp signal input terminal from the synchronous separation IC.
(with normally)
9
TDI
I
Data input terminal for ISP
10
TMS
I
M
ode input terminal for ISP
11
TCK
I
Clock input terminal for ISP
12
TEXT_HD
O
TEXT_HD output terminal
13
US_HD
I
RCA/TEXT horizontal synchronized input terminal
14
TEXT_VD
O
T
EXT_VD output terminal
15
Vcc3.3V
Power supply terminal
16
US_VD
I
RCA/TEXT vertical synchronized input terminal
17
GND
Ground
18
MODEA
I
Mode selection signal A
19
MODEB
I
Mode selection signal B
20
MODEC
I
Mode selection signal C
21
SELA
I
M
AIN
Å
EVIDEO
Å
ECHROME/ RCA HD change control signal
22
SELO
I
Synchronized signal output control signal input terminal for TEXT
23
SELC
I
HD change control signal input terminal for closed captions
24
TDO
O
Data output for ISP
25
GND
Ground
26
Vcc3.3V
Power supply terminal
27
VD1
I
MAIN 
· VIDEO 
· CHROME vertical synchronized signal input terminal from IC
28
HD1
I
MAIN 
· VIDEO 
· CHROME horizontal synchronized signal input terminal from IC
29
PL_VD
O
Vertical synchronized output terminal
30
PL_HD
O
Horizontal synchronized output terminal
31
PL_CP
O
Clamp signal output terminal
32
PL_BLK
O
H
 blank signal output terminal
33
MODED
I
Mode selection signal D
34
NC
Non connection
35
Vcc3.3V
Power supply terminal
36
NC
Non connection
37
CC_HD
O
H
orizontal synchronized signal for closed caption
38
ow_vblk
I
V
 blank signal input terminal for auto wide
39
HDS
O
Horizontal synchronized signal output terminal for PC board.
40
VDS
O
Vertical synchronized signal output terminal for PC board.
41
HD2
I
Horizontal synchronized signal input terminal from SUB 
· VIDEO 
· CHROME IC
42
VD2
I
Vertical synchronized signal input terminal from SUB
Å
EVIDEO 
· CHROME IC
43
CLK
I
C
lock input
44
NC
Non connection
61
61-1
61-2
LC-37AD1E
Ë
HISDA5550M-1Y (ASSY:IC1601)
Teletext CPU
»
Block Diagram
»
Pin Function
Pin No
.
Pin Name
I/O
Pin Function
99,1,3,4,2,100,
D0-D7
I/O
Data bus for external memory or data RAM.
98,96
97,94,93,89,86,84,
A0-A16
O
Address bus for external program memory or data RAM.
82,79,81,83,90,85,
77,78,76,71,69
70,68,67
A17-A19/
I/O
After power-on P4.0,P4.1,P4.4 work as additional address lines A17
···
19.
P4.0,P4.1,P4.4
In port mode, these port lines act as bi-directional I/O port with internal pull-up
resistors. Port pins that have '1' written to them are pulled high by the internal
pull-up resistors and in that state can be used as inputs.
9,10,11,12,13,14,
P0.0-P0.7
I/O
Port 0 is a 8-bit open drain bi-directional I/O-port. Port 0 pins that have 1
15,16
written to them float: in this state they can be used as high impedance inputs.
41,42,43,44,45,46,
P1.0-P1.7
I/O
Port is a 8-bit bi-directional multifunction I/O port with internal pull-up resistors.
47,62
(PWM)
Port 1 pins that have 1 written to them are pulled high by the internal pull-up
resistors and in that state can be used as inputs.
The secondary functions of port 1 pins are:
Port bits P1.0-P1.5 contain the 6 output channels of the 8-bit pulse width
modulation unit.
Port bits P1.6-P1.7 contain the two output channels of the 14-bit pulse width
modulation unit.
24,25,26,27
P2.0-P2.3
I
Port 2 is a 4-bit input port without pull-up resistors.
(ADC)
Port 2 also works as analog input for the 4-channel-ADC.
31,32,33,34,35,36,
P3.0-P3.7
I/O
Port 3 is an 8-bit bi-directional I/O port with internal pull-up resistors, Port 3 pins
37,38
that have 1 written to them are pulled high by the internal pull-up resistors and in
that state can be used as inputs,
To use the secondary functions of Port 3, the corresponding output latch must
be programmed to a one (1) for that function to operate. The secondary
functions are as follows:
· Alternate function
P3.0: ODD/EVEN indicate output
P3.1: external extra interrupt 0(INTX0)/UART(TXD)
P3.2: interrupt 0 input/timer 0 gate control input)INT0)
P3.3: interrupt 1 input/timer 1 gate control input)INT1)
P3.4: counter 0 input(T0)
P3.5: counter 1 input(T1) or In master mode HS or VCS output.
P3.7: external extra interrupt 0(INTX1)/UART(RXD)
48,49
P4.2-P4.3(P4.7)
I/O
Port 4 is a bi-directional I/O port with internal pull-up resistors.
Port 4 pins that have 1 written to them are pulled high by the internal pull-up
resistors and in that state can be used as inputs.
Secondary functions
P4.2: RD, Read line. This signal is same as the to output of the pin RD available
in some packages.
P4.3: WR write line. This signal is same as the output of the pin WE, which is
only available in some package.
5
XROM
I
This pin must be pulled low to access external ROM.
17
ENE
I
Enable Emulation
Only if this pin set to zero externally, STOP and OCF are operational. ENE has
an internal pull-up resistor which switches automatically to non-emulation mode
if ENE is not connected.
18
STOP
I
STOP
Emulation control line; Driving a low level during the input phase freezes the real
time relevant internal peripherals such as timers and interrupt controller.
19
OCF
O
Opcode Fetch
Emulation control line; A high level driven by the controller during output phase
indicates the beginning of a new instruction.
20
EXTIF
21
CVBS
I
CVBS input for the acquisition circuit.
29
HS/SC
I
In slave mode Horizontal sync input or sandcastle input for display
synchronization .In master mode HS or VCS output.
30
VS/P4.7
I/O
Vertical sync input/output for display synchronization.
Can also be used as digital input P4.7.
Furthermore this pin can be selected as an ODD/EVEN indicator alternatively to
P3.0.
50
RST
I
A
 low level on this pin resets the device. An internal pull-up resistor permits
power-on reset using only one external capacitor connected to Vss.
62
62-1
62-2
LC-37AD1E
Pin No
.
Pin Name
I/O
Pin Function
52
XTAL2
O
Output of the inverting oscillator amplifier.
53
XTAL1
I
Input of the inverting oscillator amplifier.
57
R
O
Red
58
G
O
Green
59
B
O
Blue
60
BLANK/COR
O
Contrast reduction and blanking.
64
WR
O
Control output; indicates a write access to the internal XRAM; can be used as a
write strobe for writing data into an external data RAM by a MOVX instruction.
This signal is also available as P4.3.
65
RD
O
Control output; indicates a read access to the internal XRAM; can be used for
latching data from the data bus into an external data RAM by a MOVX
instruction.
This signal is also available as P4.2.
72
FL_PGM
I
All the pins prefix by Flax are test pins which must be left open.
80
FL_RST
I
All the pins prefix by Flax are test pins which must be left open.
87
ALE
O
Address Latch Enable.
88
PSEN
O
Program Store Enable
is a control output signal which is usually connected to OE input line of the
external program memory to enable the data output.
95
FL_CE
I
All the pins prefix by Flax are test pins which must be left open.
6,73
VDD2.5
Supply voltage (2.5V).
22,56
VDDA2.5
Supply voltage for analog components (2.5V).
8,40,75,92
VDD3.3
Input/output (3.3V).
7,39,74,91,
VSS
Ground (0V).
23,55
VSSA
Ground for analog components.
28,51,54,61,63,66
——
Ë
HI62S8308X-1Q(ASSY:IC1603)
256K X 8-bit Low Voltage CMOS SRAM
»
Block Diagram
Pin No
.
Pin Name
I/O
Pin Function
»
Pin Function
1-4,7,
A0-A17
I
A
ddress Inputs
9-20,31
5
W
E
I
Write Enable
6
CE2
I
C
hip Enable2
8
VCC
Device Power Supply
21-23,
I/O0-I/O7
I/O
Data Inputs/Outputs
25-29
24
GND
Ground
30
CE1
I
Chip Enable1
32
OE
O
Output Enable
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