Sharp LC-32SD1E (serv.man3) Service Manual ▷ View online
LC-26SD1E/RU, LC-32SD1E/RU
7 – 13
2.5. IC2301 (VHIISL83220-1Y)
2.5.1 Block Diagram
2.5.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
15
VCC
–
System power supply input (3.0V to 5.5V).
3
V+
–
Intemally generated positive transmitter supply (+5.5V).
7
V-
–
Internally generated negative transmitter supply (-5.5V).
14
GND
–
Ground connection.
2
C1+
–
External capacitor (voltage doubler) is connected to this lead.
4
C1-
–
External capacitor (voltage doubler) is connected to this lead.
5
C2+
–
External capacitor (voltage doubler) is connected to this lead.
6
C2-
–
External capacitor (voltage doubler) is connected to this lead.
11
TIN
I
TTL/CMOS compatible transmitter inputs.
13
TOUT
O
±15KV ESD Protected, RS-232 level (nominally ±5.5V) transmitter output.
8
RIN
I
±15KV ESD Protected, RS-232 compatible receiver inputs.
9
ROUT
O
TTL/CMOS level receiver output.
1
EN
O
Active low receiver enable control; doesn't disable ROUTB output.
16
SHDN
–
Active low input shuts down transmitters and on-board power supply, to place device in low power mode.
10
N.C.
–
No internal connection.
LC-26SD1E/RU, LC-32SD1E/RU
7 – 14
2.6. IC1710 (RH-IXB823WJZZQ)
2.6.1 Block Diagram
2.6.2 Pin Connections and short description
Pin No.
Pin Name
I/O
Pin Function
NET_NAME
1
EXP [7]
O
Outport [7]
DTI2CSEL
2
EXP [6]
O
Outport [6]
DTM_RESET
3
EXP [5]
O
Outport [5]
DTV_ON
4
GND*
–
Ground
N.C.
5
EXP [3]
O
Outport [3]
BL_ON
6
GND*
–
Ground
N.C.
7
OFLOUT
O
OFL signal output
OFLOUT
8
OSCOUT
O
OSC signal output
OSCOUT
9
VCCIO1
–
VCC (3.3V)
FPGA_VCC
10
GNDIO
–
Ground
Ground.
11
GNDINT
–
ground.
Ground.
12
PCLK
I
Reference clock input
PCLK
13
VCCINT
–
VCC (3.3V)
FPGA_VCC
14
GCLR
I
RESET terminal. L: RESET, H: Normal
RESET_N
15
GND*
–
N.C.
N.C.
16
GND*
–
N.C.
N.C.
17
GND*
–
N.C.
N.C.
18
GND*
–
N.C.
N.C.
19
GND*
–
N.C.
N.C.
20
GND*
–
N.C.
N.C.
LC-26SD1E/RU, LC-32SD1E/RU
7 – 15
21
GND*
–
N.C.
N.C.
22
#TMS
I
Pin for JTAG write
FPGA_TMS
23
#TDI
I
Pin for JTAG write
FPGA_TDI
24
#TCK
I
Pin for JTAG write
FPGA_TCK
25
#TDO
O
Pin for JTAG write
FPGA_TDO
26
VSYNC
I
V sync input (not used)
V_SYNC
27
HSYNC
I
H sync input (not used)
H_SYNC
28
GND*
–
N.C.
N.C.
29
GND*
–
N.C
N.C.
30
DMY_IN
I
Dummy pin for RESET line wiring (no effect on operation)
RESET_N
31
VCCIO1
–
VCC (3.3V)
FPGA_VCC
32
GNDIO
–
Ground.
Ground.
33
GND*
–
N.C.
N.C.
34
GND*
–
N.C.
N.C.
35
SCK
I
Microprocessor control bus clock
SCK
36
GND*
–
N.C.
N.C.
37
GND*
–
N.C.
N.C.
38
GND*
–
N.C.
N.C.
39
GND*
–
N.C.
N.C.
40
GND*
–
N.C.
N.C.
41
SEN
I
Microprocessor control bus enable
SDE
42
SDA
I
Microprocessor control bus data
SDA
43
GND*
–
N.C.
N.C.
44
GND*
–
N.C.
N.C.
45
VCCIO1
–
VCC (3.3V)
FPGA_VCC
46
GNDIO
–
Ground.
Ground.
47
GND*
–
N.C.
N.C.
48
GND*
–
N.C.
N.C
49
GND*
–
N.C.
N.C.
50
GND*
–
N.C.
N.C.
51
GND*
–
N.C.
N.C.
52
GND*
–
N.C.
N.C.
53
GND*
–
N.C.
N.C.
54
GND*
–
N.C.
N.C.
55
GND*
–
N.C.
N.C.
56
GND*
–
N.C.
N.C.
57
GND*
–
N.C.
N.C.
58
GND*
–
N.C.
N.C.
59
VCCIO2
–
VCC (3.3V)
FPGA_VCC
60
GNDIO
–
Ground.
Ground.
61
GND*
–
Ground.
N.C.
62
GND*
–
Ground.
Ground.
63
VCCINT
–
VCC (3.3V)
FPGA_VCC
64
GND*
–
Ground.
Ground.
65
GNDINT
–
Ground.
Ground.
66
GND*
–
N.C.
N.C.
67
GND*
–
N.C
N.C.
68
GND*
–
N.C
N.C.
69
GND*
–
N.C
N.C.
70
GND*
–
N.C
N.C.
71
GND*
–
N.C
N.C.
72
GND*
–
N.C
N.C.
73
GND*
–
N.C
N.C.
74
GND*
–
N.C
N.C.
75
GND*
–
N.C
N.C.
76
EXP [1]
O
Outport [1]
EP1
77
GND*
–
N.C
N.C.
78
GND*
–
N.C.
N.C.
79
GNDIO
–
Ground.
Ground.
80
VCCIO2
–
VCC (3.3V)
FPGA_VCC
81
GND*
–
N.C.
N.C
82
GND*
–
N.C.
N.C
83
GND*
–
N.C.
N.C
84
GND*
–
N.C.
N.C
Pin No.
Pin Name
I/O
Pin Function
NET_NAME
LC-26SD1E/RU, LC-32SD1E/RU
7 – 16
2.7. IC704 (VHIMR4030++-1)
2.7.1 Block Diagram
2.7.2 Pin Connections and short description
85
GND*
–
N.C.
N.C
86
GND*
–
N.C.
N.C
87
GND*
–
N.C.
N.C
88
GND*
–
N.C.
N.C
89
GND*
–
N.C.
N.C
90
GND*
–
N.C.
N.C
91
EXP [4]
O
Outport [4]
PCON2 (EP4)
92
GND*
–
N.C.
N.C
93
GNDIO
–
Ground.
Ground.
94
VCCIO2
–
VCC (3.3V)
FPGA_VCC
95
GND*
–
N.C.
N.C
96
GND*
–
N.C.
N.C
97
EXP [2]
O
Outport [2]
PCON1 (EP2)
98
GND*
–
N.C
N.C
99
GND*
–
N.C.
N.C
100
EXP [0]
O
Outport [0]
S_MUTE
Pin No.
Pin Name
I/O
Pin Function
1
Z/C
I
Zero Current Detection Terminal.
2
F/B
I
Feed Back terminal.
3
GND
–
Ground Terminal.
4
VCC
–
VCC Terminal.
5
Emitter/OCL
O
Emitter/OCL terminal.
Pin No.
Pin Name
I/O
Pin Function
NET_NAME
Click on the first or last page to see other LC-32SD1E (serv.man3) service manuals if exist.