Sharp LC-32GA5E (serv.man17) Service Manual ▷ View online
101
LC-26GA5E
LC-32GA5E
LC-32GA5E
LC-26GA5E
LC-32GA5E
LC-32GA5E
1.3. Description of Pins IC1001, continued
141
NC
NC
142
656I0/YIN0
I
LV (pull
down)
down)
Digital (luminance) input [LSB]
143
VSSP9
S
Supply digital pad (0 V)
144
VDDP9
S
Supply digital pad (3.3 V)
Pin No.
Pin Name
Type
Connection
(If not used)
Short Description
PMQFP144-4
102
LC-26GA5E
LC-32GA5E
LC-32GA5E
LC-26GA5E
LC-32GA5E
LC-32GA5E
2. IC1301 (VHITA2024++-1)
2.1. Pinning
2.2. Pin Description
Pin
Function
Description
2, 3
DCAP2, DCAP1
Charge pump switching pins. DCAP1 (pin 3) is a free running 300kHz square
wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 2) is level shifted
10 volts above DCAP1 (pin 3) with the same amplitude (12Vpp nominal),
frequency, and phase as DCAP1.
wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 2) is level shifted
10 volts above DCAP1 (pin 3) with the same amplitude (12Vpp nominal),
frequency, and phase as DCAP1.
4, 9
V5D, V5A
Digital 5VDC, Analog 5VDC
5, 8,
17
AGND1, AGND2,
AGND3
Analog Ground
6
REF
Internal reference voltage; approximately 1.0 VDC.
7
OVERLOADB
A logic low output indicates the input signal has overloaded the amplifier.
10, 14
OAOUT1, OAOUT2
Input stage output pins.
11, 15
INV1, INV2
Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with
approximately 2.4VDC bias.
approximately 2.4VDC bias.
12
MUTE
When set to logic high, both amplifiers are muted and in idle mode. When low
(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. This pin should be tied to GND if not used.
(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. This pin should be tied to GND if not used.
16
BIASCAP
Input stage bias voltage (approximately 2.4VDC).
18
SLEEP
When set to logic high, device goes into low power mode. If not used, this pin
should be grounded
should be grounded
19
FAULT
A logic high output indicates thermal overload, or an output is shorted to ground,
or another output.
or another output.
20, 35
PGND2, PGND1
Power Grounds (high current)
22
DGND
Digital Ground. Connect to AGND locally (near the TA2024).
24, 27;
31, 28
OUTP2 & OUTM2;
OUTP1 & OUTM1
Bridged output pairs
25, 26,
29, 30
VDD2, VDD2
VDD1, VDD1
VDD1, VDD1
Supply pins for high current H-bridges, nominally 12VDC.
13, 21,
23, 32,
23, 32,
34
NC
Not connected. Not bonded internally.
33 VDDA
Analog
12VDC
36
CPUMP
Charge pump output (nominally 10V above VDDA)
1
5VGEN
Regulated 5VDC source used to supply power to the input section (pins 4 and 9).
FAULT
PGND2
NC
NC
VDD2
OUTM2
OUTM1
VDD1
NC
VDDA
NC
PGND1
CPUMP
DCAP2
AGND3
BIASCAP
INV2
OAOUT2
MUTE
INV1
OAOUT1
V5A
AGND2
OVERLOADB
REF
AGND1
V5D
DCAP1
30
19
20
21
22
23
24
25
26
27
28
29
1
15
14
13
11
10
12
9
8
7
6
5
4
3
2
16
17
18
+5VGEN
36
31
32
33
34
35
OUTP1
VDD1
VDD2
OUTP2
DGND
NC
SLEEP
103
LC-26GA5E
LC-32GA5E
LC-32GA5E
LC-26GA5E
LC-32GA5E
LC-32GA5E
2.3. Block Diagram
O
O
VD D A
+5VG EN
D C AP2
D C AP1
C PU M P
10
11
20
1
33
29
26
7
19
31
28
24
27
36
2
3
15
14
12
16
18
SLEEP
5V
5V
R EF
6
VDD1
PG ND1
VDD1
PG ND1
VDD2
VDD2
PG ND2
PG ND2
4
5
V5D
8
AGN D 1
AGN D 2
V5A
22
D GN D
VD D 1
PGN D 2
35
PGN D 1
VD D 2
Processing
&
M odulation
Processing
&
M odulation
9
AGN D 3
17
13
NC
21
23
25
30
32
34
VD D 1
VD D 2
104
LC-26GA5E
LC-32GA5E
LC-32GA5E
LC-26GA5E
LC-32GA5E
LC-32GA5E
4. IC6004 (RH-IXB064WJZZ)
4.1. VCT Block Diagram
4.2. Pinning
VCT 49xyI, VCT 48xyI XM
VIN9
VIN8
VIN10
VIN7
VIN6
VIN3
VIN2
VIN1
VOUT1
VOUT2
VOUT3
VSUP1.8FE
GND
VIN5
VIN4
GND
VSUP3.3FE
XROMQ
P10
P10
P11
P12
P13
P14
P15
P16
P20
P17
SDA
DFVBL / FIELD
PWMV
P21
SCL
EXTIFQ
VIN11
P37 / 656IO7
P36 / 656IO6
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
66
65
67
68
69
70
71
72
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
133
134
135
136
137
138
139
140
141
142
143
144
132
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
10
1
102
103
104
105
106
107
108
GIN
RIN
FBIN
GNDM
BIN
SVMOUT
RSW2
EW
VERT-
VERT+
RSW1
SENSE
VSUP5.0BE
TEST / SUBW
GND
GND
VREFAU
VSUP8.0AU
SPEAKERR
SPEAKERL
AOUT1L
AOUT1R
AOUT2L
AOUT2R
AIN3R
AIN3L
AIN2L
AIN2R
AIN1L
AIN1R / SIF
TAGC
VREFIF
IFIN-
IFIN+
ROUT
GOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
BOUT
VR
D
XREF
VSUP
3.
3BE
GN
D
GN
D
VS
UP3.3I
O
VS
UP3.
3DA
C
GNDDA
C
SAFET
Y
HFLB
HOUT
VPROT
ADB1
1
ADB9
ADB1
3
ADB1
4
ADB1
8
ADB1
6
ADB1
5
PS
WE
Q
ADB1
7
STO
P
Q
ENE
Q
ADB1
2
ADB7
RSTQ
ADB5
ADB4
ADB1
9
RDQ
WR
Q
OCF
ALE
ADB6
ADB8
VSU
P5.
0
F
E
P25 /
656
H
IO
P26 /
656
VIO
P30 /
656
IO
0
P31 /
656
IO
1
P32 /
656
IO
2
VSU
P3.
3EI
O
GNDEI
O
P33 /
656
IO
3
P34 /
656
IO
4
P35 /
656
IO
5
RE
SETQ
VSU
P3.
3
D
IG
GND
GND
VSU
P1.
8
D
IG
XTAL
1
XTAL
2
P22
P23
PS
ENQ
ADB1
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
ADB3
ADB2
DB0
ADB0
V
S
U
P5
.0
IF
ADB1
P24 /
656
C
L
K
IO
XTAL1
IF
Frontend
Slicer
Video
Backend
IF
Processor
Sound
Demodulator
Audio
Processor
Display
Generator
Bus
Arbiter
20kB XRAM
256kB
Prog ROM
Clock
Generator
Reset & Test
Logic
I2C Master/
Slave
24kB
Char ROM
TEST
RESETQ
XTAL2
I2C
Pxy
CVBS in
IFIN-
IFIN+
T
A
G
C
S
IF
YCbCr in
CVBS out
RGB in
A
O
U
T
S
P
E
A
K
E
R
RGB out
SVM
RGB in
SENSE
RSW
VERT
EW
HOUT
PROT
HFLB
Panorama
Scaler
Display &
Deflection
Processor
Processor
Timer
CRT
PWM
ADC
UART
Watchdog
RTC
I/O-Ports
Memory
Interface
ADB, DB, PSENQ,
PSWEQ, WRQ, RDQ
CPU
8051
A
IN
Video
Frontend
Color
Decoder
Component
Interface
Comb
Filter
656 in
656 out
S
U
B
W
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