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to  the  DDR2-667  (5-5-5)  specification. All  of  the  control  and  address  inputs  are 
synchronized with a pair of externally supplied differential clocks. Inputs are latched at the 
cross  point  of  differential  clocks  (CLK  rising  and  CLK  falling).  All I/Os  are  synchronized 
with a single ended DQS or differential DQS- DQS pair in a source synchronous fashion.

 Power Supply: VDD, VDDQ = 1.8 V± 0.1 V

 Double Data Rate architecture: two data transfers per clock cycle

 CAS Latency: 3, 4, 5, 6 and 7

 Burst Length: 4 and 8

 Bi-directional, differential data strobes (DQS andDQS ) are transmitted / received 

with data

 Edge-aligned with Read data and center-aligned with Write data

 DLL aligns DQ and DQS transitions with clock

 Differential clock inputs (CLK and CLK )

 Data masks (DM) for write data

 Commands entered on each positive CLK edge, data and data mask are 

referenced to both edges of DQS

 Posted CAS programmable additive latency supported to make command and data 

bus efficiency

 Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)

 Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for 

better signal quality

 Auto-precharge operation for read and write bursts

 Auto Refresh and Self Refresh modes

 Precharged Power Down and Active Power Down

 Write Data Mask

 Write Latency = Read Latency - 1 (WL = RL - 1)

 Interface: SSTL_18

The TDA1308 is an integrated class AB stereo headphone driver. 

 Power supply maximum 60 mW to 32Ω (THD<0.1%)

 5V single supply

 SNR 110 dB

 Power supply ripple rejection

 Typically 3 mA supply current at no load 

 No switch ON/OFF clicks 

 Excellent power supply ripple rejection

 Low power consumption



Short-circuit resistant



High performance

high signal-to-noise ratio
high slew rate
low distortion
· Large output voltage swing.

Pin configuration and description is given in Figure 16 and Table 18.

Table 18: Pin configuration                            Figure 19: Pin configuration

INB (pos) and INA (pos) are connected to a reference voltage 2.5 V by dividing VDD 

supply. INA (neg) and INB (neg) is connected to HEADPHONER, HEADPHONEL outputs 
of  VCTH.  Those  audio  outputs  are  parallel  to LINE_OUT  connectors.  Headphone  has 
also  detection  property  from  the  connector.  It  is  controlled  by  VCTH  GPIO  pin  “HP 
Detect”.

The  MSB1210  is  the  world’s  1

st

hybrid  demodulator  to  receive  both  analog 

terrestrial TV and digital TV signals. It contains the state of the art Signal Processing to 
offer high quality receptionof analog terrestrial TV signals compliant with PAL B(G, PAL I 
standards. It also contains a superior COFDM demodulator. It can be used in all 2K, 4K 
and 8K modes  with 5,6,7 and 8 MHz channels  and is capable of receiving all modes of 
transmission.

The device includes a high performance 11 bit A/D converter capable of accepting 

direct  IF  at  36 or  44  MHz.  It  can also  support  low  IF  and  ZIF  signaling.  Sampling  rates 
required  for  all  these  frequencies  in  OFDM  channels  can  be  generated  from  a  single 
24MHz crystal.