DOWNLOAD Sharp LC-26LE430E Service Manual ↓ Size: 15.96 MB | Pages: 127 in PDF or view online for FREE

         2008-03-14 

LC-19LE430E, LC-22LE430E, LC-26LE430, LC-32LE430E 

 69 

The device is controlled and configured via a hardware control interface. 

The device supports all common audio sampling rates between 8kHz and 192kHz using all common MCLK fs rates. The audio interface operates in slave 

mode. 

The WM8524 has a 3.3V tolerant digital interface, allowing logic up to 3.3V to be connected. 

The device is available in a 16pin TSSOP. 

 

· High performance stereo DAC with ground referenced line driver 

· Audio Performance 

- 106dB SNR (.A-weighted.) 

- -91dB THD @ -1dBFS 

· 120dB mute attenuation 

· All common sample rates from 8kHz to 192kHz supported 

· Hardware control mode 

· Data formats: LJ, RJ, I

2

 S 

· Maximum 1mV DC offset on Line Outputs 

· Pop/Click suppressed Power Up/Down Sequencer 

· AVDD and LINEVDD +3.3V ±10% allowing single supply 

· 16-lead TSSOP package 

· Operating temperature range: -40°C to 85°C 

 

· Consumer digital audio applications requiring 2Vrms output 

- Games Consoles 

- Set Top Box 

- A/V Receivers 

- DVD Players 

- Digital TV 

 

1.6 U501 (TMDS251PAGR TQFP64) 

The TMDS251 is a 2-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to 2 DVI or HDMI ports to be 

switched to a single display terminal. Four TMDS channels, one hot plug detector, and a digital display control (DDC) interface are supported on each port. 

Each TMDS channel supports signaling rates up to 2.5 Gbps to allow 1080p resolution in 12-bit color depth.  

The input port is enabled by configuring source selectors, S1 and S2. When an input port is selected, the TMDS inputs are connected to the TMDS outputs 

through a 2-to-1 multiplexer, the MOSFET between the input DDC channel and the output DDC channel is turned on, and the HPD output follows the state 

of the HPD_SINK. The other input port is inactive with disconnected input terminations, disconnected TMDS inputs to the outputs, disconnected DDC 

inputs to the outputs, and the HPD outputs are low state. Check the source selection look up table for the details of port selections. 

When S1 is high and S2 is low, all input terminations are disconnected, TMDS inputs are high impedance with standard TMDS terminations, all internal 

MOSFETs are turned off to disable the DDC links, and all HPD outputs are connected to the HPD_SINK. This allows the initiation of the HDMI physical 

address discovery process.  

Termination resistors (50-Ω), pulled up to VCC, are integrated at each TMDS receiver input. External terminations are not required. A precision resistor is 

connected externally from the VSADJ pin to ground for setting the differential output voltage to be compliant with the TMDS standard. 

The TMDS251 provides two levels of receiver input equalization for different ranges of cable lengths. Each TMDS receiver owns frequency responsive 

equalization circuits. When EQ sets low, the receiver supports the input connection in short range HDMI cables. When EQ sets high, the receiver supports 

the input connection in long range HDMI cables. The TMDS251 supports power saving operation. When a system is under standby mode and there is no 

digital audio/visual content from a connected source, the 3.3-V supply voltage, VCC, can be powered off to minimize power consumption from the TMDS 

inputs, outputs, and internal switching circuits. The HPD, DDC, and source selection circuits are powered up by the 5-V supply voltage, VDD, to maintain 

the system hot plug detect response, the DDC link from the selected source to the sink under system standby operation. The device is characterized for 

operation from 0°C to 70°C. 

 

LC-19LE430E, LC-22LE430E, LC-26LE430E, LC-32LE430E 

70  

· Compatible with HDMI 1.3a 

· Supports 2.5 Gbps Signaling Rate for 480i/p, 720i/p, and 1080i/p Resolutions up to 12-Bit Color Depth 

· Integrated Switchable Receiver Termination 

· Integrated Switchable Receiver Termination Accommodate to Different Input Cable Lengths 

· Intra-Pair Skew < 40 ps 

· Inter-Pair Skew < 65 ps 

· HBM ESD Protection Exceeds 8 kV to TMDS Inputs 

· 3.3-V Fixed Supply to TMDS I/Os 

· 5-V Fixed Supply to HPD, DDC, and Source Selection Circuits 

· 64-Pin TQFP Package 

· Footprint Compatible with 3-to-1 Switch TMDS351 with Port 3 Disabled 

· ROHS Compatible and 260°C Reflow Rated  

· TMDS250 is Available with Port 1 Disabled and Ports 2 and 3 Enabled 

· Supports 5-V to 3.3-V Level Shifting on DDC Links 

 

· Digital TV 

· Digital Projector 

 

1.7 U605 (CD4052BPWR TSSOP-16) 

The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage 

current. Control of analog signals up to 20VP-P can be achieved by digital signal amplitudes of 4.5V to 20V (if VDD-VSS = 3V, a VDD-VEE of up to 13V 

can be controlled; for VDD-VEE level differences above 13V, a VDD-VSS of at least 4.5V is required). For example, if VDD = +4.5V, VSS = 0V, and VEE = 

-13.5V, analog signals from -13.5V to +4.5V can be controlled by digital inputs of 0V to 5V. These multiplexer circuits dissipate extremely low quiescent 

power over the full VDD-VSS and VDD-VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic “1” is present at the 

inhibit input terminal, all channels are off. 

The CD4051B is a single 8-Channel multiplexer having three binary control inputs, A, B, and C, and an inhibit input. The three binary signals select 1 of 8 

channels to be turned on, and connect one of the 8 inputs to the output. 

The CD4052B is a differential 4-Channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 of 

4 pairs of channels to be turned on and connect the analog inputs to the outputs. The CD4053B is a triple 2-Channel multiplexer having three separate 

digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole, double-

throw configuration. 

When these devices are used as demultiplexers, the “CHANNEL IN/OUT” terminals are the outputs and the “COMMON OUT/IN” terminals are the inputs. 

· Wide Range of Digital and Analog Signal Levels 

- Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V 

- Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20VP-P 

· Low ON Resistance, 125Ω (Typ) Over 15VP-P Signal Input Range for VDD-VEE = 18V 

· High OFF Resistance, Channel Leakage of ±100pA (Typ) at VDD-VEE = 18V 

· Logic-Level Conversion for Digital Addressing Signals of 3V to 20V (VDD-VSS = 3V to 20V) to Switch Analog Signals to 20VP-P (VDD-VEE = 20V) 

· Matched Switch Characteristics, rON = 5Ω (Typ) for VDD-VEE = 15V  

· Very Low Quiescent Power Dissipation Under All Digital- Control Input and Supply Conditions, 0.2μW (Typ) at VDD-VSS = VDD-VEE = 10V 

· Binary Address Decoding on Chip 

· 5V, 10V, and 15V Parametric Ratings 

· 100% Tested for Quiescent Current at 20V 

· Maximum Input Current of 1μA at 18V Over Full Package Temperature Range, 100nA at 18V and 25oC 

· Break-Before-Make Switching Eliminates Channel Overlap 

 

         2008-03-14 

LC-19LE430E, LC-22LE430E, LC-26LE430, LC-32LE430E 

 71 

· Analog and Digital Multiplexing and Demultiplexing 

· A/D and D/A Conversion 

· Signal Gating 

 

1.8 U4051 (HY27US08561A-TPCB 256Mb TSOP1-48) 

The HYNIX HY27(U/S)S(08/16)561A series is a 32Mx8bit with spare 8Mx16 bit capacity. The device is offered in 1.8V Vcc Power Supply and in 3.3V Vcc 

Power Supply. 

Its NAND cell provides the most cost-effective solution for the solid state mass storage market. 

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. 

The device contains 2048 blocks, composed by 32 pages consisting in two NAND structures of 16 series connected Flash cells. 

A program operation allows to write the 512-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 16K-byte(X8 device) 

block. 

Data in the page mode can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command 

input. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of footprint. 

Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin. 

The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where required, and internal verification and 

margining of data. 

The modifying can be locked using the WP input pin. 

The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple memories the R/B pins can be 

connected all together to provide a global status signal. 

Even the write-intensive systems can take advantage of the HY27(U/S)S(08/16)561A extended reliability of 100K program/ erase cycles by providing ECC 

(Error Correcting Code) with real time mapping-out algorithm. 

The chip could be offered with the CE don’t care function. This function allows the direct download of the code from the NAND Flash memory device by a 

microcontroller, since the CE transitions do not stop the read operation. 

The copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly 

programmed in another page inside the same array section without the time consuming serial data insertion phase. 

This device includes also extra features like OTP/Unique ID area, Block Lock mechanism, Automatic Read at Power Up, Read ID2 extension. 

The Hynix HY27(U/S)S(08/16)561A series is available in 48 - TSOP1 12 x 20 mm , 48 - USOP1 12 x 17 mm, FBGA 9 x 11 mm. 

- Cost effective solutions for mass storage applications 

 - x8 or x16 bus width. 

- Multiplexed Address/ Data 

- Pinout compatibility for all densities 

- 3.3V device: VCC = 2.7 to 3.6V : HY27USXX561A 

- 1.8V device: VCC = 1.7 to 1.95V : HY27SSXX561A 

= (512+16) Bytes x 32 Pages x 2,048 Blocks 

= (256+8) Words x 32 pages x 2,048 Blocks 

- x8 device : (512 + 16 spare) Bytes 

: HY27(U/S)S08561A 

- x16 device: (256 + 8 spare) Words 

: HY27(U/S)S16561A 

- x8 device: (16K + 512 spare) Bytes 

- x16 device: (8K + 256 spare) Words 

LC-19LE430E, LC-22LE430E, LC-26LE430E, LC-32LE430E 

72  

- Random access: 3.3V: 12us (max.) 

1.8V: 15us (max.) 

- Sequential access: 3.3V: 50ns (min.) 

1.8V: 60ns (min.) 

- Page program time: 200us (typ.) 

- Fast page copy without external buffering 

- Block erase time: 2ms (Typ.) 

- 1st cycle : Manufacturer Code 

- 2nd cycle: Device Code 

- Simple interface with microcontroller 

- Boot from NAND support 

- Automatic Memory Download 

- Program/Erase locked during Power transitions 

- 100,000 Program/Erase cycles (with 1bit/512byte ECC) 

- 10 years Data Retention 

- HY27(U/S)S(08/16)561A-T(P) 

: 48-Pin TSOP1 (12 x 20 x 1.2 mm) 

- HY27(U/S)S(08/16)561A-T (Lead) 

- HY27(U/S)S(08/16)561A-TP (Lead Free) 

- HY27(U/S)S(08/16)561A-S(P) 

: 48-Pin USOP1 (12 x 17 x 0.65 mm) 

- HY27(U/S)S(08/16)561A-S (Lead) 

- HY27(U/S)S(08/16)561A-SP (Lead Free) 

- HY27(U/S)S(08/16)561A-F(P) 

: 63-Ball FBGA (9 x 11 x 1.0 mm) 

- HY27(U/S)S(08/16)561A-F (Lead) 

- HY27(U/S)S(08/16)561A-FP (Lead Free)