Sharp LC-24LE250EK (serv.man4) Service Manual ▷ View online
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CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in
a source synchronous fash-ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates with a single 1.5V ± 0.075V
power supply and 1.5V ± 0.075V VDDQ. The 1Gb DDR3 G-die device is available in 78ball
information in a RAS/CAS multiplexing style. The DDR3 device operates with a single 1.5V ± 0.075V
power supply and 1.5V ± 0.075V VDDQ. The 1Gb DDR3 G-die device is available in 78ball
FBGAs(x4/x8).
Table 13: Absolute Maximum DC Ratings
8. 2Gbit (256M x 8 bit) NAND Flash Memory
H27U2G8F2CTR-BC
a) Key Features
DENSITY
-2Gbit: 2048blocks
Nand FLASH INTERFACE
-NAND Interface
-ADDRESS / DATA Multiplexing
SUPPLY VOLTAGE
-Vcc = 3.0/1.8V Volt core supply voltage for Program,
Erase and Read operations.
MEMORY CELL ARRAY
-X8: (2K + 64) bytes x 64 pages x 2048 blocks
-X16: (1k+32) words x 64 pages x 2048 blocks
PAGE SIZE
-X8: (2048 + 64 spare) bytes
-X16:(1024 + 32spare) Words
Block SIZE
-X8: (128K + 4K spare) bytes
-X16:(64K + 2K spare) Words
PAGE READ / PROGRAM
-Random access: 25us (Max)
-Sequential access: 25ns / 45ns (3.0V/1.8V, min.)
-Program time(3.0V/1.8V): 200us / 250us (Typ)
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-Multi-page program time (2 pages):
200us / 250us (3.0V/1.8V, Typ.)
BLOCK ERASE / MULTIPLE BLOCK ERASE
-Block erase time:
3.5 ms (Typ)
-Multi-block erase time (2 blocks):
3.5ms/ 3.5ms (3.0V/1.8V, Typ.)
SEQURITY
-OTP area
-Serial number (unique ID)
-Hardware program/erase disabled during Power transition
-Multiplane Architecture:
Array is split into two independent planes.
Parallel operations on both planes are available, having program and erase time.
-Single and multiplane copy back program with automatic
EDC (error detection code)
-Single and multiplane page re-program
-Single and multiplane cache program
-Cache read
-Multiplane block erase
Reliability
-100,000 Program / Erase cycles (with 1bit /528Byte ECC)
-10 Year Data retention
ONFI 1.0 COMPLIANT COMMAND SET
ELECTRONICAL SIGNATURE
-Maunufacture ID: ADh
-Device ID
PACKAGE
-Lead/Halogen Free
-TSOP48 12 x 20 x 1.2 mm
-FBGA63 9 x 11 x 1.0 mm
b) Description
H27(U_S)2G8_6F2C series is a 256Mx8bit with spare 8Mx8 bit capacity. The device is offered in
3.0/1.8 Vcc Power Supply, and with x8 and x16 I/O interface Its NAND cell provides the most
cost-effective solution for the solid state mass storage market. The memory is divided into blocks that
can be erased independently so it is possible to preserve valid data while old data is erased.
cost-effective solution for the solid state mass storage market. The memory is divided into blocks that
can be erased independently so it is possible to preserve valid data while old data is erased.
The device contains 2048 blocks, composed by 64 pages. Memory array is split into 2 planes, each
of them consisting of 1024 blocks. Like all other 2KB -page NAND Flash devices, a program operation
allows to write the 2112-byte page in typical 200us(3.3V) and an erase operation can be performed in
typical 3.5ms on a 128K-byte block. In addition to this, thanks to multi-plane architecture, it is possible
allows to write the 2112-byte page in typical 200us(3.3V) and an erase operation can be performed in
typical 3.5ms on a 128K-byte block. In addition to this, thanks to multi-plane architecture, it is possible
to program 2 pages at a time (one per each plane) or to erase 2 blocks at a time (again, one per each
plane). As a consequence, multi-plane architecture allows program time to be reduced by 40% and
erase time to be reduction by 50%. In case of multi-plane operation, there is small degradation at 1.8V
application in terms of program/erase time.
plane). As a consequence, multi-plane architecture allows program time to be reduced by 40% and
erase time to be reduction by 50%. In case of multi-plane operation, there is small degradation at 1.8V
application in terms of program/erase time.
The multiplane operations are supported both with traditional and ONFI 1.0 protocols. Data in the
page can be read out at 25ns (3V version) and 45ns (1.8V version) cycle time per byte. The I/O pins
serve as the ports for address and data input/output as well as command input. This interface allows a
reduced pin count and easy migration towards different densities, without any rearrangement of
serve as the ports for address and data input/output as well as command input. This interface allows a
reduced pin count and easy migration towards different densities, without any rearrangement of
footprint. Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and
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CLE input pin. The on-chip Program/Erase Controller automates all read, program and erase functions
including pulse repetition, where required, and internal verification and margining of data.
including pulse repetition, where required, and internal verification and margining of data.
A WP# pin is available to provide hardware protection against program and erase operations.
The output pin RB# (open drain buffer) signals the status of the device during each operation. In a
system with multiple memories the RB# pins can be connected all together to provide a global status
signal. Each block can be programmed and erased up to 100,000 cycles with ECC (error correction
signal. Each block can be programmed and erased up to 100,000 cycles with ECC (error correction
code) on. To extend the lifetime of Nand Flash devices, the implementation of an ECC is mandatory.
The chip supports CE# don't care function. This function allows the direct download of the code from
the NAND Flash memory device by a microcontroller, since the CE# transitions do not stop the read
operation. In addition, device supports ONFI 1.0 specification.
The chip supports CE# don't care function. This function allows the direct download of the code from
the NAND Flash memory device by a microcontroller, since the CE# transitions do not stop the read
operation. In addition, device supports ONFI 1.0 specification.
The copy back function allows the optimization of defective blocks management: when a page
program operation fails the data can be directly programmed in another page inside the same array
section without the time consuming serial data insertion phase. Copy back operation automatically
executes embedded error detection operation: 1 bit error out of every 528-byte (x8) or 1 bit error out of
section without the time consuming serial data insertion phase. Copy back operation automatically
executes embedded error detection operation: 1 bit error out of every 528-byte (x8) or 1 bit error out of
every 264-word (x16) can be detected. With this feature it is no longer necessary to use an external to
detect copy back operation errors. Multiplane copy back is also supported, both with traditional and
ONFI 1.0 protocols. Data read out after copy back read (both for single and multiplane cases) is
detect copy back operation errors. Multiplane copy back is also supported, both with traditional and
ONFI 1.0 protocols. Data read out after copy back read (both for single and multiplane cases) is
allowed. In addition, Cache program and multi cache program operations improve the programming
throughput by programming data using the cache register.
throughput by programming data using the cache register.
The devices provide two innovative features: page re-program and multiplane page re program. The
page re-program allows to re-program one page. Normally, this operation is performed after a
previously failed page program operation. Similarly, the multiplane page reprogram allows to
re-program two pages in parallel, one per each plane. The first page must be in the first plane while the
second page must be in the second plane; the multiplane page re-program operation is performed after a
previously failed multiplane page program operation. The page re-program and multiplane page
re-program two pages in parallel, one per each plane. The first page must be in the first plane while the
second page must be in the second plane; the multiplane page re-program operation is performed after a
previously failed multiplane page program operation. The page re-program and multiplane page
re-program guarantee improve performance, since data insertion can be omitted during re-program
operations, and save ram buffer at the host in the case of program failure. The devices, available in the
TSOP48 (12X20mm) package, support the ONFI1.0 specification and come with four sequrity features:
operations, and save ram buffer at the host in the case of program failure. The devices, available in the
TSOP48 (12X20mm) package, support the ONFI1.0 specification and come with four sequrity features:
-OTP (one time programmable) area, which is a restricted access area where sensitive data/code
can be stored permantely.
-Serial number (unique identifier), which allows the devices to be uniquely indentified.
-Read ID2 extension
-Read ID2 extension
These security features are subject to an NDA (non-disclosure agreement) and are, therefore, no
described in the datasheet. For more details about them, contact your nearest Hynix sales office.
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9. 16M-BIT [16M x 1] CMOS SERIAL FLASH EEPROM
MX25L1602 Mstar SPI Flash
a) Key Features
■ HIGH DENSITY NAND FLASH MEMORIES GENERAL
•
16,777,216 x 1 bit structure
•
256 Equal Sectors with 8K-byte each -Any sector can be erased
•
4096 Equal Segments with 512-byte each -Provides sequential output within any segment
•
Single Power Supply Operation -3.0 to 3.6 volt for read, erase, and program operations
•
Latch-up protected to 100mA from -1V to Vcc +1V
•
Low Vcc write inhibit is equal to or less than 2.5V
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