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2.2.   IC 306 (MSH 9000-LF)

2.2.1. Functional Block Diagram

 

EN

Bandgap

Digital Control

MUTE

5V Regulator

GND

AVDD

UVP

VIPL

VINL

PGA

Modulator

Output Driver

OCP

HVSSL

HVDDL

FBPL

FBNL

G0

G1

OUTPL

OUTNL

PGA

Modulator

VIPR

VINR

Output Driver

OCP

HVSSR

HVDDR

FBPR

FBNR

OUTPR

OUTNR

2.2.   IC 306 (MSH 9000-LF)

2.2.2. Pin Description

Analog Interface 

VIPL Analog 

Input 

Left 

channel P side audio input 

3 

VINL 

Analog Input 

Left channel N side audio input 

4 

VINR 

Analog Input 

Right channel N side audio input 

7 

VIPR 

Analog Input 

Right channel P side audio input 

8 

OUTNR Analog 

Output 

Right 

channel 

N side switching output 

12, 14 

OUTPR Analog 

Output 

Right 

channel 

P side switching output 

17, 19 

FBPR 

Analog Output 

Right channel P side feedback 

22 

FBNR 

Analog Output 

Right channel N side feedback 

23 

FBNL 

Analog Output 

Left channel N side feedback 

28 

FBPL 

Analog Output 

Left channel P side feedback 

29 

OUTPL Analog 

Output 

Left 

channel P side switching output 

32, 34 

OUTNL Analog 

Output 

Left 

channel 

N side switching output 

37, 39 

 

Digital Interface 

G0 

Digital Input 

Volume gain control bit 0 

5 

G1 

Digital Input 

Volume gain control bit 1 

2 

MUTE Digital 

Input 

Class-D is mute when EN=Hi 

6 

EN 

Digital Input 

Class-D is enable when EN=Hi 

26 

 

Power Pins 

HVSSL Ground Ground 

for 

left channel 

1, 30, 31, 
40 

HVSSR Ground Ground 

for 

right channel 

10, 11, 20, 
21 

HVDDR 

Analog Input 

Supply voltage for Right channel 

13, 15, 16, 
18 

HVDDL 

Analog Input 

Supply voltage for Left channel 

33, 35, 36, 
38 

AVDD Analog 

Input 

Internal 

reference 

voltage 

25 

GND Ground 

Ground 

9, 

24 

2.3.  IC 1001 (MSD3303GX)

2.3.1. Key Features

• Master CPU with MMU.
• DRAM controller supporting up to two 16-bit DDR2 interface.
• Power control module with ultra low power MCU available in stand by mode.
• Parallel interface for external parallel NOR fl ash and NAND fl ash support.
• H.264 decoder. Support resolution up to HDTV ( 1080i, 720p) .
• MPEG-2 decoder.
• Video analog processor.
• NTSC/PAL/SECAM Video Decoder.
• Support Teletext mode.
• Two CVBS video outputs.
• Eight confi gurable CVBS, Y/C, S-video inputs.
• Multistandard sound Processor.
• AC3 decoder.
• I²S digital audio output.
• Six L/R audio line-inputs.
• SIF audio output.
• Stereo L/R output for main speaker.
• Two HDMI / HDCP compliant input port. 
• CEC support.
• Fully programmable scaler and display processing.
• Support up to 10 bit LVDS full HDTV panel interface.
• Support USB 2.0
• Support Common Interface for conditional access.

2.3.2. Block Diagram

TRANSPORT

DEMUX

MPEG2/

MPEG4

NTSC/PAL/

SECAM

DECODER

SIF

DEMOD

AUDIO

DSP

ANALOG

FRONT-END

INPUT

PROCESSING

DEINTERLACE

and SCALING

VIDEO

OUTPUT

CONTROLLER

AUDIO

OUTPUT

CONTROLLER

DDR2-16x2

DRAM I/F

Processor *2

USB 2.0

HOST *2

/YPBPR x3

-VIDEO x8

IN (1P, 1S)

I2S INx1

PDIF IN x1

DDR-2 DRAM

I2CS, JTAG I/F

UART: x3

I2CM: x1

SPI: x1 (2 cs)

PWM: x4

PFLH: x1

DVB-CI: x1

PHY I/F

Dual LVDS

L/R OUT x3

S/PDIF OUT

VIDEO

PROCESSING

GRAPHICS

ENGINE

SIF IN x1

BS OUT x2

I2S OUT

TV Encoder

DAC

Power

Management

IR, CEC, INT,  

HSYNC, SARx4

HW JPD

ADC

L/R x6

ADC

AUDIO

DSP

VIDEO 

PROCES

SING

H.264/

RM

MII or RMII

10/100M

EMAC

2.3.  IC 1001 (MSD3303GX)

2.3.3. Pin Description 

Analog Interface   

VCLAMP  

CVBS/YC 

Mode 

Clamp Voltage Bypass 

K4 

REFP 

 

Internal ADC Top De-coupling Pin 

H4 

REFM 

 

Internal ADC Bottom De-coupling Pin 

J4 

REXT 

Analog Input 

External Resister 390 ohm to AVDD_33 

G4 

HSYNC0 Schmitt 

Trigger 

Input 

w/ 5V-tolerant 

HSYNC / Composite Sync for VGA Input from channel 0 

N2 

VSYNC0 Schmitt 

Trigger 

Input 

w/ 5V-tolerant 

VSYNC for VGA Input from channel 0 

N1 

HSYNC1 Schmitt 

Trigger 

Input 

w/ 5V-tolerant 

HSYNC / Composite Sync for VGA Input from channel 1 

K3 

VSYNC1 Schmitt 

Trigger 

Input 

w/ 5V-tolerant 

VSYNC for VGA Input from channel 1 

K2 

HSYNC2 Schmitt 

Trigger 

Input 

w/ 5V-tolerant 

HSYNC for VGA Input from channel 2 

J5 

BINM 

Analog Input 

Reference Ground for Analog Blue Input 

T3 

BIN0P 

Analog Input 

Analog Blue Input from Channel 0 

R1 

BIN1P 

Analog Input 

Analog Blue Input from Channel 1 

K1 

BIN2P 

Analog Input 

Analog Blue Input from Channel 2 

U1 

GINM 

Analog Input 

Reference Ground for Analog Green Input 

R2 

GIN0P 

Analog Input 

Analog Green Input from Channel 0 

R3 

GIN1P 

Analog Input 

Analog Green Input from Channel 1 

L3 

GIN2P 

Analog Input 

Analog Green Input from Channel 2 

V2 

SOGIN0 

Analog Input 

Sync On Green Input from Channel 0 

P3 

SOGIN1 

Analog Input 

Sync On Green Input from Channel 1 

L2 

SOGIN2 

Analog Input 

Sync On Green Input from Channel 2 

V3 

RINM 

Analog Input 

Reference Ground for Analog Red Input 

P1 

RIN0P 

Analog Input 

Analog Red Input from Channel 0 

P2 

RIN1P 

Analog Input 

Analog Red Input from Channel 0 

L1 

RIN2P 

Analog Input 

Analog Red Input from Channel 0 

V1 

Analog Video Input/Output Interface 

CVBS7 

Analog Input 

CVBS (Composite) Video Input Channel 7 

M3 

CVBS6 

Analog Input 

CVBS (Composite) Video Input Channel 6 

M2 

CVBS5 

Analog Input 

CVBS (Composite) Video Input Channel 5 

N3 

CVBS4 

Analog Input 

CVBS (Composite) Video Input Channel 4 

M1 

CVBS3 

Analog Input 

CVBS (Composite) Video Input Channel 3 

T1 

CVBS2 

Analog Input 

CVBS (Composite) Video Input Channel 2 

U2 

CVBS1 

Analog Input 

CVBS (Composite) Video Input Channel 1 

U3 

CVBS0 

Analog Input 

CVBS (Composite) Video Input Channel 0 

W1 

VCOM1 

Analog Input 

CVBS Input Reference Ground 

T2 

VCOM0 

Analog Input 

CVBS Input Reference Ground 

Y3 

CVBSOUT0 Analog 

Output  CVBS (Composite) Video Output Channel 0 

Y2 

CVBSOUT1 Analog 

Output  CVBS (Composite) Video Output Channel 1 

AA2