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The tuner, whose RF circuit is composed of FET and whose local oscillation circuit, mixing circuit, IF amplifier
circuit and PLL circuit are composed of 1-chip IC, is 2-in-1 construction which has IF signal processing circuit
built in.
The channel selection circuit is of PLL frequency synthesizer type under the control of I2C bus. The receiving
frequency range is from 44.25 to 863.25 MHz, which can cover almost all VHF, UHF and CATV channels.
The IF signal processing circuit of the split carrier type employs the video PLL synchro system.
For video, a 1Vp-p composite signal is outputted from the terminal No. 19 (Video).  For audio, a SIF signal is
outputted from the terminal No. 15 (SIF).

21
ANT

HPF

BPF RF AMP

BPF

RF AMP

T.BPF

MIX

OSC

LPF

SAW

VIF

AMP

VIDEO

DET

FM DET AF AMP

EQ

AMP

SAW

IF AMP

MIX

I

2

C PLL

OSC

MIX-PLL IC

T.BPF

VHF SECTION

AGC

1

AS

3

SCL

4

SDA

5

MB

6

BP

7

BT

9

IF OUT

11

SIF

AMP

AGC

AFT

18

MUTE

17

SIF 
OUT   15

AUDIO
OUT   16

VIDEO
OUT   19

The audio signal processing circuit is mainly composed of a 1-chip digital audio signal processing circuit (IC3304),
an active filter circuit (IC3301-IC3303) and an audio amplifying IC (IC3305).
Controlling of IC3304 is all under microprocessor control (I

2

C bus control, port control).

The SIF signal sent from the tuner is amplified in the SIF amplifying circuit composed of Q3201 and Q3202 and
is inputted to pin (87) (ANA_IN+ terminal) of IC3304.  Then, after being A/D-converted, it is subjected to FM
detecting and sound multiplex decoding (NICAM/IGR) in digital signal processing.
The TV audio signal and the audio input signal for three systems (video: 2, component: 1) A/D-converted in
IC3304 are switched in the IC, subjected to volume controlling and equalizer correction (for acoustic character-
istic correction) and then outputted from pins (27) and (28) as analog signals after being D/A converted.
The audio signal outputted from pins (27) and (28) of IC3304 is subjected to acoustic characteristic correction in
the active filter circuit composed of IC3301, IC3302 (used in 13/15 only) and IC3303, audio-amplified in IC3305
and then outputted through J3500 (headphone jack) to the speaker.
The analog audio signal outputted from pins (36) and (37) of IC3304 is subjected to V2 audio I/O switching in
IC3501 and outputted from the AV2 terminal (AV2 terminal output mode).

AV1

S-VIDEO

INPUT

AV2

INPUT

OUTPUT

COMPONENT

INPUT

AUDIO

IN/OUT

SWITCH

IC3501

Q3500

AUDIO

DECODER

(MSP)

IC3304

L2, R2

DL, DR

L1, R1

I

2

C

AUDIO

FILTER

IC3301

IC3303

IC3302

Model

13/15

DC POWER

AUDIO

AMPLIFIER

IC3305

HEAD

PHONE

JACK

SP-L

SP-R

The video signal processing circuit is a multi video system that is mainly composed of a digital video signal
processing IC (IC801).
The TV video signal sent from the tuner and the V1 video input signal and V2 video input signal inputted through
each input terminal are switched in IC402 and inputted to pin (73) of IC801.  The Y/C signal inputted to the S
terminal is inputted to pins (71) and (72) of IC801.
The AV2 terminal is capable of I/O switching and controlled by Q3501 thru Q3505.

AV1

S-VIDEO

INPUT

V1

V2

AV2

INPUT

OUTPUT

VIDEO

SWITCH

IC402

V

SY, SC

VIDEO

IN/OUT

SWITCH

Q3501-

Q3503

V0

CVIN

CSYNC0

BUFFER

Q402

BUFFER

Q401

SYNC

SEPARATER.

IC401

MPU

IC2001

VOUT

I

2

C

3.3V REG.

VIDEO

DECODER

(VPC)
IC801

LCD

PANEL

AD-converted 
data is inputted.

Data, clock, etc. 
are inputted.

OSD data etc. is inputted.

1-3. GRAY LEVEL
CIRCUIT

1-5. LCD

CONTROLLER

CIRCUIT

RGB-converted 
data is outputted.

Gray level reference 
voltages and electrode 
signals are outputted.

The video signal or Y/C signal inputted to IC801 is AD-converted in the IC and subjected to various video
adjustments in digital signal processing.  As a Y/UV digital signal (ITU-R601 format) the Y data is outputted from
pins (31) thru (34) and (37) thru (40) and the C data (UV data) is outputted from pins (41) thru (44) and (47) thru
(50), and then they are inputted to the LCD controller circuit.

CIN

VIN1

VIN2

VIN3

VIN4

VOUT

RGB/

YCrCb

RGB/

YCrCb

FB

Analog

Front-end

AGC

2

×

ADC

Analog

Component

Front-end

4

×

ADC

Processing

Matrix

Contrast

Saturation

Brightness

Tint

Adaptive

Comb

Filter

NTSC

PAL

Color

Decoder

NTSC

PAL

SECAM

Saturation

Tint

Mixer

2D Scaler

PIP

Pehorame

Mode

Contrast

Brightness

Peaking

Output

Formatter

ITU-R656
ITU-R601

Memory

Control

Y

Cr

Cb

Y

Cr

Cb

Y/G

Y

Cr

Cb

FB

U/B

V/R

FB

Y OUT

Cr Cb
OUT

YCOE

FIFO
CNTL

LL Clock

H Sync

V Sync

AVO

I

2

C Bus

I

2

C Bus

Clock
Gen.

Sync

+

Clock

Generation

20.25MHz

The component signal from the analog board is inputted to the input port (

4

,

5

,

6

) of IC801 (video decoder).

The video signal (pin (70)) outputted from IC801 is subjected to sync separation in Q401 (buffer) and IC401
(sync separator) and then inputted to the CSYNC port (

6

) of IC2001.

The component signal inputted to IC801 is AD-converted in the IC and then inputted to IC1201 (LCD controller).
From CVIN and CSYNC inputted to IC2001, CK, VD, HD, OSD-RGB, MPCLK, MPDA and MPCS are outputted
to IC1201.  At the same time, MPDA and MPCLK are inputted to the gray level circuit.
The component signal inputted to IC1201 is RGB-converted in the IC and then outputted to the LCD panel.  At
the same time, GCK is inputted to IC1203, IC1204 and IC1205 (gate control) and then outputted to the LCD
panel.

BUFFER

Q402

SYNC

SEPARATER.

IC401

BUFFER

Q401

COMPONENT

INPUT

YPbPr

VIDEO

DECODER

(VPC)
IC801

I

2

C

Y, PB, PR

VOUT

3.3V REG.

CSYNC0

CVIN

MPU

IC2001

Data, clock, etc. are inputted.

AD-converted 
data is inputted.

1-5. LCD

CONTROLLER

CIRCUIT

LCD

PANEL

RGB-converted
data is outputted.

OSD data etc. is inputted.

1-3. GRAY

LEVEL

CIRCUIT

Gray level reference 
voltages and electrode 
signals are outputted.

The Y/UV signal from IC801 and the VD, HD, BK, CK and OSD-RGB signals for OSD inputted to pins (95), (97),
(21), (17) and (32) thru (34) from IC2001 are subjected to RGB conversion, PAL pixel skipping 7-6 line conver-
sion and 8-6 bit conversion in IC1201 and then outputted as RGB 6-bit data to the LCD panel (R0-5: pins (89)
thru (86), G0-5: pins (98) thru (93), B0-5: pins (108) thru (103)).
The LCD controller also outputs the timing signal at the time of vertical and horizontal reverse display control
and light control.

VIDEO

DECODER

IC801

FIFO

IC1202

LCD

CONTROLLER

IC1201

GATE

CONTROL

IC1203
IC1204
IC1205

MPU

IC2001

VSY, HSY, FIELD, VACT,
UV0-7 (

7

–

0

)

R0-5 (

q

–

r

), G0-5, B0-5

CK, SPIO, SPOI, LBR, HG

CK, VD, HD, OSD-RGB

GCK

GCK

MPCS, MPCLK, MPDA

VP_Y0-7 (

3

–

6

)

LCD

PANEL

~ 3

 thru 

r

 are waveform measurement points.