Sharp 76FW-53H (serv.man13) Service Manual ▷ View online
Colour Television – DA100/DW100 Chassis
Sharp Electronics (UK) Ltd
Technical Support
September 99
Page 10
V Prot Signal
V
ERTICAL
F
LY
-
BACK
At the point where vertical fly-back is initiated Q503 turns off and Q502 turns on allowing +25v to flow
from Q502 emitter to the field scan coils. Since there is –13v on the other side of the scan coils
derived from the vertical drive signal, we effectively have 38v across the field coils, which will force the
electron beam to the top of the screen.
from Q502 emitter to the field scan coils. Since there is –13v on the other side of the scan coils
derived from the vertical drive signal, we effectively have 38v across the field coils, which will force the
electron beam to the top of the screen.
The vertical drive signal that is outputted from IC801 pin 31 has a negative going pulse in addition to
the normal ramp waveform. This negative pulse is used to initiate vertical fly-back. This drive signal is
applied to the emitter of Q505 via R508. The potential divider R526 and R514 will fix Q505 base
voltage so that it will only turn on during the period of the negative going pulse. Once Q505 turns on
its collector voltage will fall turning on Q507 taking its emitter to ground, which results in:
the normal ramp waveform. This negative pulse is used to initiate vertical fly-back. This drive signal is
applied to the emitter of Q505 via R508. The potential divider R526 and R514 will fix Q505 base
voltage so that it will only turn on during the period of the negative going pulse. Once Q505 turns on
its collector voltage will fall turning on Q507 taking its emitter to ground, which results in:
Q503 turns off due to the removal of gate bias
Q502 turns on allowing +25v at the junction of Q502 collector and the scan coils due to the action
D507 conducting secondly enabling D507 to conduct.
Q502 turns on allowing +25v at the junction of Q502 collector and the scan coils due to the action
D507 conducting secondly enabling D507 to conduct.
From the Junction Q502 collector and
the scan coils the vertical fly-back pulse
is applied to IC801 pin 11 (Vprot Signal)
as an indicator of vertical output stage
operation. If IC801 cannot detect the
negative edge of this pulse the IC801 will
presume that the vertical stage is not
operating correctly and blank the RGB
drive.
the scan coils the vertical fly-back pulse
is applied to IC801 pin 11 (Vprot Signal)
as an indicator of vertical output stage
operation. If IC801 cannot detect the
negative edge of this pulse the IC801 will
presume that the vertical stage is not
operating correctly and blank the RGB
drive.
+25v
+5v
VProtect
Field Scan Coils
R526
4k7
4k7
R514
390
390
R508
680
680
Q505
R528
100k
100k
R504
39k
39k
Q507
R547
3k9
3k9
C512
220nF
220nF
R505
2k2
2k2
R506
120
120
R517
15k
15k
R507
8k2
8k2
D507
12v
12v
Q502
D508
Q503
Drive
Field Output
Colour Television – DA100/DW100 Chassis
Sharp Electronics (UK) Ltd
Technical Support
September 99
Page 11
VIDEO AND SYNC PROCESSOR
This IC is a member of the ‘Micronas’ VDP 31xxB IC family, which are high-quality video processors
Allowing the economic integration of features in all classes of TV sets. The VDP 31xxB family is
based on functional blocks contained in the two previous chips form Micronas:
Allowing the economic integration of features in all classes of TV sets. The VDP 31xxB family is
based on functional blocks contained in the two previous chips form Micronas:
VPC 3200A Video Processor
DDP 3300A Display and Deflection Processor
DDP 3300A Display and Deflection Processor
VDP 31xxB contains the entire video, display, and deflection processing for 4:3 and 16:9 CTV’s
operating at either 50 or 60Hz featuring:
operating at either 50 or 60Hz featuring:
2H adaptive Comb-filter
Scan Velocity Modulator.
1H Comb-filter
Colour Transient Improvement.
RGB Insertion
Tube Control
Programmable RGB Matrix
4 composite inputs (one for S-VHS)
Composite video & sync output
Horizontal scaling (0.25 to 4)
Panorama vision
Black level expander
Dynamic peaking
Soft-limiter (gamma correction)
Picture frame generator
High-performance H/V deflection
Separate ADC for tube measurements
EHT compensation
One 20.25 MHz crystal (for all systems), few external components
Embedded RISC controller (80 MIPS)
I
Scan Velocity Modulator.
1H Comb-filter
Colour Transient Improvement.
RGB Insertion
Tube Control
Programmable RGB Matrix
4 composite inputs (one for S-VHS)
Composite video & sync output
Horizontal scaling (0.25 to 4)
Panorama vision
Black level expander
Dynamic peaking
Soft-limiter (gamma correction)
Picture frame generator
High-performance H/V deflection
Separate ADC for tube measurements
EHT compensation
One 20.25 MHz crystal (for all systems), few external components
Embedded RISC controller (80 MIPS)
I
2
C-Bus Interface
Single 5 V power supply
D
ESCRIPTION
A
NALOGUE FRONT
-
END
This block provides the analogue interfaces to all video inputs and mainly carries out analogue-to
digital conversion for the following digital video processing.
digital conversion for the following digital video processing.
Most of the functional blocks in the front-end are digitally controlled (clamping, AGC, and clock-DCO).
The control loops are closed by the Fast Processor (‘FP’) embedded in the decoder.
The control loops are closed by the Fast Processor (‘FP’) embedded in the decoder.
I
NPUT
S
ELECTOR
Up to five analogue inputs can be connected. Four inputs are for input of composite video or S-VHS
luma signal. These inputs are clamped to the sync back porch and are amplified by a variable gain
amplifier. One input is for connection of S-VHS chrominance signal. This input is internally biased and
has a fixed gain amplifier.
luma signal. These inputs are clamped to the sync back porch and are amplified by a variable gain
amplifier. One input is for connection of S-VHS chrominance signal. This input is internally biased and
has a fixed gain amplifier.
C
LAMPING
The composite video input signals are AC coupled to the IC. The clamping voltage is stored on the
coupling capacitors and is generated by digitally controlled current sources. The clamping level is the
back porch of the video signal. S-VHS chroma is also AC coupled. The input pin is internally biased to
the centre of the ADC input range.
coupling capacitors and is generated by digitally controlled current sources. The clamping level is the
back porch of the video signal. S-VHS chroma is also AC coupled. The input pin is internally biased to
the centre of the ADC input range.
Colour Television – DA100/DW100 Chassis
Sharp Electronics (UK) Ltd
Technical Support
September 99
Page 12
A
UTOMATIC
G
AIN
C
ONTROL
A digitally working automatic gain control adjusts the magnitude of the selected base-band by +6/–4.5
dB in 64 logarithmic steps to the optimal range of the ADC. The gain of the video input stage including
the ADC is 213 steps/V with the AGC set to 0 dB.
dB in 64 logarithmic steps to the optimal range of the ADC. The gain of the video input stage including
the ADC is 213 steps/V with the AGC set to 0 dB.
A
NALOGUE
-
TO
-D
IGITAL
C
ONVERTERS
Two ADCs are provided to digitise the input signals. Each converter runs with 20.25 MHz and has 8
bit resolution. An integrated band-gap circuit generates the required reference voltages for the
converters.
bit resolution. An integrated band-gap circuit generates the required reference voltages for the
converters.
D
IGITALLY
C
ONTROLLED
C
LOCK
O
SCILLATOR
The clock generation is also a part of the analogue front end. The crystal oscillator is controlled
digitally by the control processor; the clock frequency can be adjusted within
digitally by the control processor; the clock frequency can be adjusted within
±
150 ppm.
A
NALOGUE
V
IDEO
O
UTPUT
The input signal of the Luma ADC is available at the analogue video output pin. A source follower
must buffer the signal at this pin. The output voltage is 2 V, thus the signal can be used to drive a 75
must buffer the signal at this pin. The output voltage is 2 V, thus the signal can be used to drive a 75
Ω
line. The magnitude is adjusted with an AGC in 8 steps together with the main AGC.
A
VERAGE
B
EAM
C
URRENT
L
IMITING
The average beam current limiter (BCL) uses the sense input for the beam current measurement. The
BCL uses a different filter to average the beam current during the active picture. The filter bandwidth
is approximately. 2 kHz.
BCL uses a different filter to average the beam current during the active picture. The filter bandwidth
is approximately. 2 kHz.
The beam current limiter has an automatic offset adjustment that is active two lines before the first
cut-off measurement line.
cut-off measurement line.
The beam current limiter allows the setting of a threshold current. If the beam current is above the
threshold, the excess current is low-pass filtered and used to attenuate the RGB outputs by adjusting
the white-drive multipliers for the internal (digital) RGB signals, and the analogue contrast multipliers
for the analogue RGB inputs, respectively.
threshold, the excess current is low-pass filtered and used to attenuate the RGB outputs by adjusting
the white-drive multipliers for the internal (digital) RGB signals, and the analogue contrast multipliers
for the analogue RGB inputs, respectively.
The lower limit of the attenuator is programmable, thus a minimum contrast can always be set. During
the CRT measurement, the ABL attenuation is switched off. After the white drive measurement line it
takes 3 lines to switch back to BCL limited drives and brightness.
the CRT measurement, the ABL attenuation is switched off. After the white drive measurement line it
takes 3 lines to switch back to BCL limited drives and brightness.
P
ROTECTION
C
IRCUITRY
‘Vertical fly-back’ and the ‘Safety’ inputs provide picture tube and drive stage protection.
Vertical fly-back;
This pin searches for a negative edge in every field, otherwise the RGB
drive signals are blanked. Drive shutoff during fly-back: this feature can be
selected by software.
drive signals are blanked. Drive shutoff during fly-back: this feature can be
selected by software.
Safety;
Input pin: this input has two thresholds. Between zero and the lower
threshold, normal functioning takes place. Between the lower and the
higher threshold, the RGB signals are blanked. Above the higher
threshold, the RGB signals are blanked and the horizontal drive is shut off.
threshold, normal functioning takes place. Between the lower and the
higher threshold, the RGB signals are blanked. Above the higher
threshold, the RGB signals are blanked and the horizontal drive is shut off.
Both thresholds have a small hysteresis. The main oscillator and the
horizontal drive circuitry are run from a separate (standby) power supply
and are already active while the TV set is powering up.
horizontal drive circuitry are run from a separate (standby) power supply
and are already active while the TV set is powering up.
Note:
In the DA100 and DW100 chassis the standby supply pin is connected to VCC.
S
CAN
V
ELOCITY
M
ODULATION
O
UTPUT
This output delivers the analogue SVM signal. The D/A converter is a current sink like the RGB D/A
converters. At zero signal level the output current is 50% of the maximum output current.
converters. At zero signal level the output current is 50% of the maximum output current.
Colour Television – DA100/DW100 Chassis
Sharp Electronics (UK) Ltd
Technical Support
September 99
Page 13
PICTURE ROTATION
Due to the width of a 16:9 CRT the horizontal tilt of the picture can be influence by external magnetic
fields.
fields.
To overcome this problem, an extra coil is fitted around the CRT, which is connected between the
junction of Q1603/Q1604 emitter and ground.
junction of Q1603/Q1604 emitter and ground.
The microprocessor (IC1001) will output a PWM signal from pin 55. This signal is then passed
through a LPF and fed to an error amplifier (IC601). The output from this error amp can swing from a
positive to a negative voltage depending on the mark space ratio of the PWM signal from IC1001.
through a LPF and fed to an error amplifier (IC601). The output from this error amp can swing from a
positive to a negative voltage depending on the mark space ratio of the PWM signal from IC1001.
Under normal conditions (CRT is not effected by external magnetic fields) there will be no output from
the error amplifier, therefore, both Q1603 and Q1604 are turned off causing no current to flow through
the coil around the CRT neck. However if the output from the error amplifier is positive then Q1603
will turn on allowing current to flow from the +13v rail, through the coil to ground. If the error amplifier
output is negative going then Q1604 will turn on, allowing current to flow from ground to the –13v rail.
the error amplifier, therefore, both Q1603 and Q1604 are turned off causing no current to flow through
the coil around the CRT neck. However if the output from the error amplifier is positive then Q1603
will turn on allowing current to flow from the +13v rail, through the coil to ground. If the error amplifier
output is negative going then Q1604 will turn on, allowing current to flow from ground to the –13v rail.
The end user has control of this adjustment via the picture menu.
Note
The location of this circuit can vary between 66cm models (Located on CRT base) and 76cm
models (located on sub PWB).
models (located on sub PWB).
+
-
1kHz PWM
IC1001, pin 55
IC1001, pin 55
R1620
10k
10k
R1619
100k
100k
C1608
10
10
R1617
2k2
2k2
D1607
2v4
2v4
C1609
10
10
R1618
100k
100k
R1616
100k
100k
C1610
100nF
100nF
IC1601
C1611
10nF
10nF
R1615
1M
1M
R1624
100
100
R1622
470
470
Q1603
Q1604
-13v
R1623
100
100
R1621
100
100
+13v
C1613
220
220
C1612
220
220
Tilt Coils
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