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V

CC

DC Supply Voltage

±

20

V

T

stg

, T

j

Storage and Junction Temperature

–40 to 150

°C

V

FREQ

Maximum Voltage Across VFREQ (Pin 9)

8

V

T

op

Operating Temperature Range

-20 to 70

°C

ESD

Maximum ESD on Pins

±

1.8

kV

R

th j-amb

Thermal Resistance Junction to ambient

80

°C/W

R

th j-pin

Thermal Resistance Junction to Pin                                                  Max.

12

°C/W

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20

-V

CC

-V

CC

-V

CC

OUT

BOOTDIODE

BOOT

NC

FEEDCAP

FREQUENCY

SGN-GND

IN

ST-BY-MUTE

NC

+V

CC 

SIGN

VREG

+V

CC

 POW

-V

CC

-V

CC

-V

CC

-V

CC

NEGATIVE SUPPLY.
NEGATIVE SUPPLY.
NEGATIVE SUPPLY.
PWM OUTPUT
BOOTSTRAP DIODE ANODE
BOOTSTRAP CAPACITOR
NOT CONNECTED
FEEDBACK INTEGRATING CAPACITANCE
SETTING FREQUENCY RESISTOR
SIGNAL GROUND
INPUT
ST-BY/ MUTE CONTROL PIN
NOT CONNECTED
POSITIVE SIGNAL SUPPLY
10V INTERNAL REGULATOR
POSITIVE POWER SUPPLY
NEGATIVE SUPPLY (TO BE CONNECTED TO PIN 16 VIA C5)
NEGATIVE SUPPLY
NEGATIVE SUPPLY
NEGATIVE SUPPLY

-V

CC

OUT

BOOTDIODE

N.C.

BOOT

FEEDCAP

FREQ

1

3

2

4

5

6

7

8

9

STBY/MUTE

N.C.

+V

CC SIGN

+V

CC POW

VREG

-V

CC 

-V

CC

20

19

18

17

16

14

15

13

12

D96AU537B

SGN-GND

10

IN

11

-V

CC

-V

CC

-V

CC

-V

CC

PIN CONNECTION (Top view)

0

4

8

12

Area(cm

2

)

30

40

50

60

R

thj-a

(˚C/W)

D97AU675

COPPER AREA 35

µ

THICKNESS

PC BOARD

ELECTRICAL CHARACTERISTICS (Refer to the test circuit, V

CC

 = 

±

14V; R

L

 = 8

Ω

; R

S

 = 50

Ω

;

R

f

 = 12K

Ω

; Demod.. filter L = 60

µ

H, C = 470nF; f = 1KHz; T

amb

 = 25°C unless otherwise specified.)

V

S

Supply Range

±

10

±

16

V

I

q

Total Quiescent Current

R

L

 = 

∞

; NO LC Filter

25

40

mA

V

OS

Output Offset Voltage

Play Condition

–50

+50

mV

P

O

Output Power

THD = 10%
THD = 1%

8.5

6

10

7

W
W

R

L

 = 4

Ω

  V

CC

 = 

±

10.5V

THD = 10%
THD = 1%

10

7

W
W

P

d

 (*)

Dissipated Power at 1W Output
Power

R

f

 = 12K

Ω 

P

Ο

 = 1W  

1

W

P

DMAX

Maximum Dissipated Power

P

Ο

 = 10W  THD 10%

R

th-j-amb

 = 38°C/W (Area 12cm

2

)

1.8

W

η

Efficiency

 ≡

  

P

O

P

O

 

+

 P

D

 

≡

 

P

O

P

I

  (**)

THD 10%
R

th-j-amb

 = 38°C/W (Area 12cm

2

)

80

85

%

THD

Total Harmonic Distortion

R

L

  = 8

Ω

; P

O

 = 0.5W

0.1

%

I

max

Overcurrent Protection
Threshold

R

L

 = 0

3.5

5

A

T

j

Thermal Shut-down Junction
Temperature

150

°C

G

V

Closed Loop Gain

29

30

31

dB

e

N

Total Input Noise

A Curve
f = 20Hz to 22KHz

7

12

µ

V

µ

V

R

i

Input Resistance

20

30

K

Ω

SVR

Supply Voltage Rejection

f = 100Hz; V

r

 = 0.5

46

60

dB

T

r

, T

f

Rising and Falling Time

50

ns

R

DSON

Power Transistor on Resistance

0.4

Ω

F

SW

Switching Frequency

100

120

140

KHz

F

SW_OP

Switching Frequency Operative
Range

100

200

KHz

B

F

Zero Signal Frequency
Constant  (***)

1.4x10

9

Hz

Ω

R

F

Frequency Controller Resistor
Range  (****)

7

12

14

K

Ω

V

ST-BY

Stand-by range

0.8

V

V

MUTE

Mute Range

1.8

2.5

V

V

PLAY

Play Range (1)

4

V

A

MUTE

Mute Attenuation

60

80

dB

I

qST-BY

Quiescent Current @ Stand-by

3

5

mA

*: The output average power when the amplifier is playing music can be considered roughly 1/10 of the maximum output power. So it is useful
    to consider the dissipated power in this condition for thermal dimensioning.

**: P

O

 = measured across the load using the following inductor: 

     COIL 58120 MPPA2  (magnetics)        TURNS: 28

 ∅

 1mm

     COIL77120 KOOL M

µ  

(magnetics)     TURNS: 28

 ∅ 

1mm

***: The zero-signal switching frequency can be obtained using the following expression: F

SW

 = B

F

/R

F

****: The maximum value of R

F

 is related to the maximum possible value for the voltage drop on R

F

 itself.

(1): For V

12

 >5.2V, an input impedance of 10K

Ω

 is to be considered.

Block Diagram of the MSP 34x1G

80-pin PQFP package

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

AVSUP

AVSUP

ANA_IN1+

ANA_IN

−

ANA_IN2+

TESTEN

XTAL_IN

XTAL_OUT

TP

AUD_CL_OUT

NC

NC

D_CTR_I/O_1

D_CTR_I/O_0

ADR_SEL

STANDBYQ

CAPL_M

AHVSUP

CAPL_A

SC1_OUT_L

SC1_OUT_R

VREF1

SC2_OUT_L

SC2_OUT_R

NC

NC

DACM_SUB

NC

DACM_L

DACM_R

VREF2

DACA_L

NC

AVSS

AVSS

MONO_IN

NC

VREFTOP

SC1_IN_R

SC1_IN_L

ASG1

NC

SC2_IN_R

SC2_IN_L

ASG2

SC3_IN_R

SC3_IN_L

ASG4

SC4_IN_R

SC4_IN_L

NC

AGNDC

AHVSS

AHVSS

NC

NC

I2C_CL

I2C_DA

I2S_CL

I2S_WS

I2S_DA_OUT

I2S_DA_IN1

ADR_DA

ADR_WS

ADR_CL

NC

DVSUP

DVSUP

DVSUP

DVSS

DVSS

DVSS

I2S_DA_IN2

NC

NC

NC

RESETQ

NC

NC

DACA_R

T

A

Ambient Operating Temperature

−

0

70

1)

°

C

T

S

Storage Temperature

−

−

40

125

°

C

V

SUP1

First Supply Voltage

AHVSUP

−

0.3

9.0

V

V

SUP2

Second Supply Voltage

DVSUP

−

0.3

6.0

V

V

SUP3

Third Supply Voltage

AVSUP

−

0.3

6.0

V

dV

SUP23

Voltage between AVSUP 
and DVSUP

AVSUP,
DVSUP

−

0.5

0.5

V

P

TOT

Power Dissipation
PLCC68
PSDIP64
PSDIP52
PQFP80
PLQFP64

AHVSUP,
DVSUP, 
AVSUP

1200
1300
1200
1000
  960

1)

mW
mW
mW
mW
mW

V

Idig

Input Voltage, all Digital Inputs

−

0.3

V

SUP2

+

0.3

V

I

Idig

Input Current, all Digital Pins

−

−

20

+

20

mA

2)

V

Iana

Input Voltage, all Analog Inputs

SCn_IN_s,

3)

MONO_IN

−

0.3

V

SUP1

+

0.3

V

I

Iana

Input Current, all Analog Inputs

SCn_IN_s,

3)

MONO_IN

−

5

+

5

mA

2)

I

Oana

Output Current, all SCART Outputs

SCn_OUT_s

3)

4)

, 

5)

4)

, 

5)

I

Oana

Output Current, all Analog Outputs 
except SCART Outputs

DACp_s

3)

4)

4)

I

Cana

Output Current, other pins 
connected to capacitors

CAPL_p,

3)

AGNDC

4)

4)

1)

PLQFP64: 65 

°

C

2)

positive value means current flowing into the circuit

3)

“n” means “1”, “2”, “3”, or “4”,     “s” means “L” or “R”,    “p” means “M” or “A”

4)

The analog outputs are short-circuit proof with respect to First Supply Voltage and ground.

5)

Total chip power dissipation must not exceed absolute maximum rating.