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K9356M: 

Standard 
B/G, D/K, I, L 
Features 
TV IF audio filter with pass band for sound carriers at 32,40 MHz (D/K, L), 32,90 MHz (I) and 33,40 MHz 
(B/G) 
Terminal and Pin configuration are the same with 

K3953M

 

 

K9656M: 

Standard 
B/G, D/K, I, L/L’ 
Features 
TV IF audio filter with two channels 
Channel 1 (L’) with one pass band for sound carriers at 40,40 MHz (L’) and 39,75 MHz (L’- NICAM) 
Channel 2 (B/G, D/K, L, I) with one pass band for sound carriers between 32,35 MHz and 33,40 MHz 
Terminal and Pin configuration are the same with 

K3953M

 

 

LM317T TDA1308T 
MSP3410G VDP3130Y 
TEA6415 STV9379FA 
TDA7269A LM7805/LM7808 
24C08 SDA55XX 
MC44608 TCET1102G 
TDA9885T 
 

The LM317T is an adjustable 3 terminal positive voltage regulator capable of supplying in excess of 1.5 
amps over an output range of 1.25 to 37 volts. This voltage regulator is exceptionally easy to use and 
requires only two external resistors to set the output voltage. Further, it employs internal current limiting, 
thermal shutdown and safe area compensation, making it essentially blow–out proof. The LM317 
serves a wide variety of applications including local, on card regulation. This device can also be used to 
make a programmable output regulator, or by connecting a fixed resistor between the adjustment and 
output, the LM317 can be used as a precision current regulator. 

• Output Current in Excess of 1.5 A 
• Output Adjustable between 1.2 V and 37 V 
• Internal Thermal Overload Protection 
• Internal Short Circuit Current Limiting Constant with Temperature 
• Output Transistor Safe–Area Compensation 
• Floating Operation for High Voltage Applications 
• Available in Surface Mount D

2

PAK, and Standard 3–Lead Transistor Package 

• Eliminates Stocking many Fixed Voltages 
 

The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic 
package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for 
portable digital audio applications. It gets its input from two analog audio outputs (DACA_L and 
DACA_R) of MSP 34x0G. The gain of the output is adjustable by the feedback resistor between the 
inputs and outputs. 

• 

Wide temperature range 

• 

No switch ON/OFF clicks 

• 

Excellent power supply ripple rejection 

• Low power consumption 
• Short-circuit resistant 
• High performance 
• high signal-to-noise ratio 
• High slew rate 
• Low distortion 
• Large output voltage swing. 

 

 
SYMBOL PIN 

OUTA 1 

Output 

A 

INA(neg) 

2 

Inverting input A 

INA(pos) 

3 

Non-inverting input A 

V

SS

 4 

Negative 

supply 

INB(pos) 

5 

Non-inverting input B 

INB(neg) 

6 

Inverting input B 

OUTB 7 

Output 

B 

V

DD

 8 

Positive 

supply 

 

The MSP 34x0G family of single-chip Multi standard Sound Processors covers the sound processing of 
all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound 
processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on 
a single chip. Figure shows a simplified functional block diagram of the MSP 34x0G. 

evaluated internally with subsequent switching between mono/stereo/bilingual; no I

2

C interaction is 

necessary (Automatic Sound Selection). 

 
This new generation of TV sound processing ICs now includes versions for processing the multi 
channel television sound (MTS) signal conforming to the standard recommended by the Broadcast 
Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, MICRONAS Noise 
Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM 
multiplex standard (EIA-J) and the FM Stereo Radio standard. Current ICs have to perform adjustment 
procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x0G has 
optimum stereo performance without any adjustments. 
All MSP 34x0G versions are pin and software downward compatible to the MSP34x0D. The 
MSP34x0G further simplifies controlling software. Standard selection requires a single I

2

C transmission 

only. 
The MSP 34x0G has built-in automatic functions: The IC is able to detect the actual sound standard 
automatically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be 

Standard Selection with single I

2

C transmission  

Automatic Standard Detection of terrestrial TV standards  
Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS  
Two selectable sound IF (SIF) inputs  
Automatic Carrier Mute function 
Interrupt output programmable (indicating status change)  
Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness  
AVC: Automatic Volume Correction  
Subwoofer output with programmable low-pass and complementary high-pass filter  
5-band graphic equalizer for loudspeaker channel  
Spatial effect for loudspeaker channel 
Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs  
Complete SCART in/out switching matrix  
Two I

2

S inputs; one I

2

S output  

Dolby Pro Logic with DPL 351xA coprocessor 
All analog FM-Stereo A2 and satellite standards; AM-SECAM L standard 
Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM  
Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification)  
ASTRA Digital Radio (ADR) together with DRP 3510A  
All NICAM standards 
Korean FM-Stereo A2 standard 

NC = not connected; leave vacant 
LV = if not used, leave vacant 
X = obligatory; connect as described in circuit diagram 
DVSS: if not used, connect to DVSS 
AHVSS: connect to AHVSS 
 

Pin No. 

Pin Name 

Type 

Connection 
(if not used) 

Short Description 

PLCC 
68-pin 

PSDIP 
64-pin 

PSDIP 
52-pin 

PQFP 
80-pin 

PLQFP 
64-pin 

 

 

 

 

1 16 

14 9 8  ADR_WS  OUT 

LV 

ADR 

word 

strobe 

2 - -  - -  NC 

 

LV 

Not 

connected 

3 15 

13 8 7  ADR_DA  OUT 

LV 

ADR 

Data 

Output 

4 14 

12 7 6  I2S_DA_IN1 

 

IN  LV 

I

2

S1 data input 

5 13 

11 6 5  I2S_DA_OUT 

 

OUT 

LV 

I

2

S data output 

6 12 

10 5 4  I2S_WS  IN/OUT 

LV 

I

2

S word strobe 

7 11 

9 4 

3 I2S_CL 

  IN/OUT 

LV 

I

2

S clock 

8 10 

8 3 

2 I2C_DA  IN/OUT 

X 

I

2

C data 

9  9 7  2 1  I2C_CL 

IN/OUT 

X 

I

2

C data 

10 8 -  1 64 NC 

 

LV 

Not 

connected 

11 7  6 

80 63  STANDBYQ 

IN  X 

Stand-by 

(low-active) 

12 6  5 

79 62  ADR_SEL  IN  X 

I

2

C bus address select 

13 5  4 

78 61  D_CTR_I/O_0 

IN/OUT 

LV 

D_CTR_I/O_0 

14 4  3 

77 60  D_CTR_I/O_1 

IN/OUT 

LV 

D_CTR_I/O_1 

15 3  - 

76 59  NC 

 

LV 

Not 

connected 

16 2  - 

75 58  NC 

 

LV 

Not 

connected 

17 

- -  - -  NC 

 

LV 

Not 

connected 

18 1  2 

74 57  AUD_CL_OUT 

OUT LV 

Audio clock output  
(18.432 MHz) 

19  64 1 

73 56  TP 

 

LV 

Test 

pin 

20  63 52  72 55  XTAL_OUT OUT X 

Crystal 

oscillator 

21  62 51  71 54  XTAL_IN 

IN  X 

Crystal 

oscillator 

22  61 50  70 53  TESTEN 

IN  X 

Test 

pin 

23  60 49  69 52  ANA_IN2+  IN 

AVSS via 56 
pF/LV 

IF Input 2 (can be left 
vacant, only if IF input 1 is 
also not in use) 

24  59 48  68 51  ANA_IN- 

IN 

AVSS via 56 
pF/LV 

IF common (can be left 
vacant, only if IF input 1 is 
also not in use) 

25  58 47  67 50  ANA_IN1+  IN  LV 

IF 

input 

2 

26 

57 

46 

66 

49 

AVSUP 

 

X 

Analog power supply 5v 

- 

- 

- 

65 

- 

AVSUP 

 

X 

Analog power supply 5v 

- - 

- 64 

- NC 

  LV 

Not 

connected 

- - 

- 63 

- NC 

  LV 

Not 

connected 

27  56 45  62 48  AVSS 

 

X 

Analog 

ground 

- - 

- 61 

- AVSS 

  X 

Analog 

ground 

28  55 44  60 47  MONO_IN  IN  LV 

Mono 

input 

- - 

- 59 

- NC 

  LV 

Not 

connected 

29  54 43  58 46  VREFTOP   

X 

Reference voltage IF A/D 
converter 

30  53 42  57 45  SC1_IN_R  IN  LV 

SCART 

1 

input, 

right 

31 

52 

41 

56 

44 

SC1_IN_L 

IN 

LV 

SCART 1 input, left 

32 

51 

- 

55 

43 

ASG1 

 

AHVSS 

Analog Shield Ground 1 

33  50 40  54 42  SC2_IN_R  IN  LV 

SCART 

2 

input, 

right 

34 

49 

39 

53 

41 

SC2_IN_L 

IN 

LV 

SCART 2 input, left 

35 

48 

- 

52 

40 

ASG2 

 

AHVSS 

Analog Shield Ground 2 

36  47 38  51 39  SC3_IN_R  IN  LV 

SCART 

3 

input, 

right 

37 

46 

37 

50 

38 

SC3_IN_L 

IN 

LV 

SCART 3 input, left 

38 

45 

- 

49 

37 

ASG4 

 

AHVSS 

Analog Shield Ground 4 

39  44 - 

48 36  SC4_IN_R  IN  LV 

SCART 

4 

input, 

right 

40 

43 

- 

47 

35 

SC4_IN_L 

IN 

LV 

SCART 4 input, left 

41 

- 

- 

46 

- 

NC 

 

LV or AHVSS 

Not connected 

42  42 36  45 34  AGNDC 

 

X 

Analog 

reference 

voltage 

43  41 35  44 33  AHVSS 

 

X 

Analog 

ground 

- - 

- 43 

- AHVSS    X 

Analog 

ground 

- - 

- 42 

- NC 

  LV 

Not 

connected 

- - 

- 41 

- NC 

  LV 

Not 

connected 

44  40 34  40 32  CAPL_M 

 

X 

Volume 

capacitor 

MAIN 

45 

39 

33 

39 

31 

AHVSUP 

 

X 

Analog power supply 8V 

46  38 32  38 30  CAPL_A 

 

X 

Volume 

capacitor 

AUX 

47 

37 

31 

37 

29 

SC1_OUT_L 

OUT 

LV 

SCART output 1, left 

48 

36 

30 

36 

28 

SC1_OUT_R 

OUT 

LV 

SCART output 1, right 

49  35 29  35 27  VREF1 

 

X 

Reference 

ground 

1 

50 

34 

28 

34 

26 

SC2_OUT_L 

OUT 

LV 

SCART output 2, left 

51 

33 

27 

33 

25 

SC2_OUT_R 

OUT 

LV 

SCART output 2, right 

52 

- 

- 32 

- NC 

  LV 

Not 

connected 

53  32 - 

31 24  NC 

 

LV 

Not 

connected 

54  31 26  30 23  DACM_SUB 

OUT LV 

Subwoofer 

output 

55  30 - 

29 22  NC 

 

LV 

Not 

connected 

56  29 25  28 21  DACM_L 

OUT LV 

Loudspeaker 

out, 

left 

57  28 24  27 20  DACM_R  OUT LV 

Loudspeaker 

out, 

right 

58  27 23  26 19  VREF2 

 

X 

Reference 

ground 

2 

59  26 22  25 18  DACA_L 

OUT LV 

Headphone 

out, 

left 

60  25 21  24 17  DACA_R 

OUT LV 

Headphone 

out, 

right 

- - 

- 23 

- NC 

  LV 

Not 

connected 

- - 

- 22 

- NC 

  LV 

Not 

connected 

61  24 20  21 16  RESETQ 

IN  X 

Power-on-reset 

62  23 - 

20 15  NC 

 

LV 

Not 

connected 

63  22 - 

19 14  NC 

 

LV 

Not 

connected 

64  21 19  18 13  NC 

 

LV 

Not 

connected 

65  20 18  17 12  I2S_DA_IN2 

IN  LV 

I

2

S2-data input 

66  19 17  16 11  DVSS 

 

X 

Digital 

ground 

- - 

- 15 

- DVSS 

  X 

Digital 

ground 

- - 

- 14 

- DVSS 

  X 

Digital 

ground 

67  18 16  13 10  DVSUP 

 

X 

Digital 

power 

supply 

5V 

- - 

- 12 

- DVSUP    X 

Digital 

power 

supply 

5V 

- - 

- 11 

- DVSUP    X 

Digital 

power 

supply 

5V 

68  17 15  10 9 

ADR_CL 

OUT LV 

ADR 

clock 

 

The VDP 313xY is a video IC family of high-quality single-chip video processors. Modular design and a 
sub-micron technology allow the economic integration of features in all classes of TV sets. The VDP 
313xY family is based on the VDP 31xxB including YC

R

C

B 

inputs for DVD component signals. 

The VDP 313xY includes complete video, display and deflection processing. All processing is done 
digitally, the video front-end and video backend are interfacing to the analog world. Most functions of 
the VDP can be controlled by software via I

2

C-Bus interface