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11AK45 is a 50Hz colour television capable of driving 24” + CRT sizes (beginning from 24” 16:9 up to 
33”). 
The chassis is capable of operation in PAL, SECAM, NTSC (playback) colour standards and multiple 
transmission standards as B/G, D/K, I/I’, and L/L´. 
Sound system output is supplying 2x10W (10%THD) for left and right outputs of 8ohm speakers. 
TV supports FASTTEXT. It is possible to decode transmissions including high graphical data. 
The chassis is equipped with three full EuroScarts; only one of them supports RGB input, one 
headphone output, one FAV input, one SVHS input (via SCART) 
 

The hardware and software of the TV is suitable for tuners, supplied by different companies, which are 
selected from the Service Menu. These tuners can be combined VHF, UHF tuners suitable for CCIR 
systems B/G, H, L, L´, I/I´, and D/K. The tuning is available through the digitally controlled I

2

C bus 

(PLL). Below you will find info on one of the Tuners in use. 
 
General description of UV1316: 
The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range 
of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. The 
low IF output impedance has been designed for direct drive of a wide variety of SAW filters with 
sufficient suppression of triple transient.  

Features of UV1316: 
1.  Member of the UV1300 family small sized UHF/VHF tuners 
2.  Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K 
3.  Digitally controlled (PLL) tuning via I

2

C-bus 

4.  Off-air channels, S-cable channels and Hyperband 
5.  World standardized mechanical dimensions and world standard pinning 
6. Compact 

size 

7.  Complies to “CENELEC EN55020” and “EN55013” 

 

Pinning: 
1. 

Gain control voltage (AGC)  : 

4.0V, Max: 4.5V 

2. Tuning 

voltage 

3. 

I²C-bus address select   

: 

Max: 5.5V 

4. 

I²C-bus serial clock  

 

: 

Min:-0.3V, Max: 5.5V 

5. 

I²C-bus serial data   

 

: 

Min:-0.3V, Max: 5.5V 

6. Not 

connected 

7. 

PLL supply voltage  

 

: 

5.0V, Min: 4.75V, Max: 5.5V 

8. ADC 

input 

9. 

Tuner supply voltage 

 

: 

33V, Min: 30V, Max: 35V 

10.  Symmetrical IF output 1 
11.  Symmetrical IF output 2 
 

The TDA9885 is an alignment-free single standard (without positive modulation) vision and sound IF signal 
PLL.  
The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL 
Both devices can be used for TV, VTR, PC and set-top box applications. 
The following figure shows the simplified block diagram of the integrated circuit.  
The integrated circuit comprises the following functional blocks:  
VIF amplifier, Tuner and VIF-AGC, VIF-AGC detector, Frequency Phase-Locked Loop (FPLL) detector, VCO 
and divider, Digital acquisition help and AFC, Video demodulator and amplifier, Sound carrier trap, SIF 
amplifier, SIF-AGC detector, Single reference QSS mixer, AM demodulator, FM demodulator and acquisition 
help, Audio amplifier and mute time constant, I

2

C-bus transceivers and MAD (module address), Internal 

voltage stabilizer. 

 

In case of three or more external sources are used, the video switch IC TEA6415 is used. The main 
function of this device is to switch 8 video-input sources on the 6 outputs. 
Each output can be switched on only one of each input. On each input an alignment of the lowest level 
of the signal is made  (bottom of sync. top for CVBS or black level for RGB signals). 
Each nominal gain between any input and output is 6.5dB.For D2MAC or Chroma signal the alignment 
is switched off by forcing, with an external resistor bridge, 5VDC on the input. Each input can be used 
as a normal input or as a MAC or Chroma input (with external Resistor Bridge). All the switching 
possibilities are changed through the BUS. Driving 75ohm load needs an external resistor. It is possible 
to have the same input connected to several outputs. 
 

The MSP 34x10G family of single-chip Multi-standard Sound Processors covers the sound processing 
of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound 
processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on 
a single chip. 
The DBX noise reduction, or alternatively, MICRONAS Noise Reduction (MNR) is performed alignment 
free. 

 

The TDA7269A is class AB dual Audio power amplifier assembled in the Multi-watt package, specially 
designed for high quality sound application as Hi-Fi music centers and stereo TV sets. 
 

The IC STV9379FA is the vertical deflection booster circuit. Two supply voltages, +14V and –14V are 
needed to scan the inputs VERT+ and VERT-, respectively. And a third supply voltage, +60V for the 
flyback limiting is needed. The vertical deflection coil is connected in series between the output and 
feedback to the input.  
 

The TDA6108Q includes three video output amplifiers is intended to drive the three cathodes of a 
colour picture tube. 

u

ll pagewidth

MHC108

DIGITAL VCO CONTROL

AFC DETECTOR

RC VCO

VIF-PLL

VIF-AGC

TUNER AGC

SUPPLY

SIF-AGC

AUDIO PROCESSING

AND SWITCHES

NARROW-BAND

FM-PLL DEMODULATOR

SINGLE REFERENCE QSS MIXER

INTERCARRIER MIXER

AND AM DEMODULATOR

SOUND CARRIER

TRAPS

4.5 to 6.5 MHz

TAGC

CVAGC(pos)

CAGC(neg)

CBL

VAGC

(1)

TOP

14 (15)

VPLL

19 (21)

9 (8)

16 (17)

15 (16)

21 (23)

4 (2)

10 (9)

11 (10)

12 (11)

18 (20)

20 (22)

2 (31)

1 (30)

(18) 17

(7) 8

(3) 5

(4) 6

external reference signal

or 4 MHz crystal

REF

AFC

AUD

CVBS

audio output

video output: 2 V (p-p)
[1.1 V (p-p) without trap]

CAF

SIOMAD

SDA

SCL

MAD

VP

CAGC

(6, 12, 13, 14, 17,
19, 25, 28, 29, 32)
13

n.c.

AGND

7 (5)

DGND

OUTPUT

PORTS

I

2

C-BUS TRANSCEIVER

22 (24)

3 (1)

OP1

OP2

FMPLL

DEEM

AFD

sound intercarrier output

and MAD select

FM-PLL

filter

VIF-PLL

filter

de-emphasis

network

VIF2

VIF1

24 (27)

23 (26)

SIF2

SIF1

(1) Not connected for TDA9885.

Pin numbers for TDA9885HN and TDA9886HN in parenthesis.

The DC voltages required at various parts of the chassis are provided by an SMPS transformer 
controlled by the IC MC44608, which is designed for driving, controlling and protecting switching 

transistor

  of  SMPS. The  transformer  generates  145V for Horizontal output stage, +/-14V for audio 

amplifier, 5V and 3.3V stand by voltage and 8V, 12V and 5V supplies for other different parts of the chassis. 

An optocoupler is used to control the regulation of line voltage and stand-by power consumption. There 
is a regulation circuit in secondary side. This circuit produces a control voltage according to the 
changes in 145V DC voltage, via an optocoupler (TCET1102G) to pin3 of the IC. 
During the switch on period of the transistor, energy is stored in the transformer. During the switch off 
period energy is fed to the load via secondary winding. By varying switch-on time of the power 
transistor, it 

 controls  each  portion  of  energy  transferred  to the secondary side such that the output 

voltage level remains nearly independent of load variations.  
 

10.1.General Features 
• Feature selection via special function register 
• Simultaneous reception of TTX, VPS, PDC, and WSS (line 23) 
• Supply Voltage 2.5 and 3.3 V 
• ROM version package PSDIP52-2, PMQFP64-1 
• Romless version package PMQFP100-2, PLCC84-2 
 
10.2.External Crystal and Programmable Clock Speed 
• Single external 6MHz crystal, all necessary clocks are generated internally 
• CPU clock speed selectable via special function registers. 
• Normal Mode 33.33 MHz CPU clock, Power Save mode 8.33 MHz 
 
10.3.Microcontroller Features 
• 8bit 8051 instruction set compatible CPU. 
• 33.33-MHz internal clock (max.) 
• 0.360 ms (min.) instruction cycle 
• Two 16-bit timers 
• Watchdog timer 
• Capture compare timer for infrared remote control decoding 
• Pulse width modulation unit (2 channels 14 bit, 6 channels 8 bit) 
• ADC (4 channels, 8 bit) 
• UART (rxd, txd) 
 
10.4.Memory 
• Non-multiplexed 8-bit data and 16 … 20-bit address bus (ROMless Version) 
• Memory banking up to 1Mbyte (Romless version) 
• Up to 128 Kilobyte on Chip Program ROM 
• Eight 16-bit data pointer registers (DPTR) 
• 256-bytes on-chip Processor Internal RAM (IRAM) 
• 128bytes extended stack memory. 
• Display RAM and TXT/VPS/PDC/WSS-Acquisition-Buffer directly accessible via MOVX 
• UP to 16KByte on Chip Extended RAM (XRAM) consisting of; 
- 1 Kilobyte on-chip ACQ-buffer-RAM (access via MOVX) 
- 1 Kilobyte on-chip extended-RAM (XRAM, access via MOVX) for user software 
- 3 Kilobyte Display Memory 
 
10.5.Display Features 
• ROM Character Set Supports all East and West European Languages in single device 
• Mosaic Graphic Character Set 
• Parallel Display Attributes 
• Single/Double Width/Height of Characters 
• Variable Flash Rate 
• Programmable Screen Size (25 Rows x 33...64 Columns) 
• Flexible Character Matrixes (HxV) 12 x 9...16 
• Up to 256 Dynamical Redefinable Characters in standard mode; 1024 Dynamical Redefinable 
Characters in Enhanced Mode 
• CLUT with up to 4096 colour combinations 

• Up to 16 Colours per DRCS Character 
• One out of Eight Colours for Foreground and Background Colours for 1-bit DRCS and ROM 
Characters 
• Shadowing 
• Contrast Reduction 
• Pixel by Pixel Shiftable Cursor With up to 4 Different Colours 
• Support of Progressive Scan and 100 Hz. 
• 3 X 4Bits RGB-DACs On-Chip 
• Free Programmable Pixel Clock from 10 MHz to 32MHz 
• Pixel Clock Independent from CPU Clock 
• Multinorm H/V-Display Synchronization in Master or Slave Mode 
 
10.6.Acquisition Features 
• Multi-standard Digital Data Slicer 
• Parallel Multi-norm Slicing (TTX, VPS, WSS, CC, G+) 
• Four Different Framing Codes Available 
• Data Caption only limited by available Memory 
• Programmable VBI-buffer 
• Full Channel Data Slicing Supported 
• Fully Digital Signal Processing 
• Noise Measurement and Controlled Noise Compensation 
• Attenuation Measurement and Compensation 
• Group Delay Measurement and Compensation 
• Exact Decoding of Echo Disturbed Signals 
 
10.7.Ports 
• One 8-bit I/O-port with open drain output and optional I

2

C Bus emulation support (Port0) 

• Two 8-bit multifunction I/O-ports (Port1, Port3) 
• One 4-bit port working as digital or analogue inputs for the ADC (Port2) 
• One 2-bit I/O port with secondary function (P4.2, 4.3, 4.7) 
• One 4-bit I/O-port with secondary function (P4.0, 4.1, 4.4) (Not available in P-SDIP 52) 
 

The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package. 
The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital 
audio applications. 
 

K3953M: 

Standard 
B/G, D/K, I, L/L’

 

Features 
TV IF filter with Nyquist slopes at 33,90 MHz and 38,90 MHz 
Constant group delay 
Suitable for CENELEC EN 55020 
Terminals 
Tinned CuFe alloy 
Pin configuration 
1 Input 
2 Input - ground 
3 Chip carrier - ground 
4 Output 
5 Output 

 
K3958M: 

Standard 
B/G, D/K, I, L/L’ 
Features 
TV IF filter with Nyquist slopes at 33.90 MHz and 38.90 MHz 
Constant group delay 
Terminal and Pin configuration are the same with 

K3953M