DOWNLOAD Sharp 21HS-50 (serv.man4) Service Manual ↓ Size: 116.98 KB | Pages: 10 in PDF or view online for FREE

ndbook, full pagewidth

SUPPLY

MANAGEMENT

internal

supply

UVLO

start

M-level

VCC

1

2

3

GND

S1

CTRL

FREQUENCY

CONTROL

VOLTAGE

CONTROLLED

OSCILLATOR

LOGIC

LOGIC

OVER-

VOLTAGE

PROTECTION

OVERPOWER
PROTECTION

short

winding

soft

start

S2

OVER-

TEMPERATURE

PROTECTION

S

Q

R

UVLO

Q

MAXIMUM

ON-TIME

PROTECTION

POWER-ON

RESET

−

1

VALLEY

100 mV

clamp

DRIVER

START-UP

CURRENT SOURCE

0.75 V

0.5 V

5

Isense

6

DRIVER

MGU230

4

DEM

8

DRAIN

7

HVS
n.c.

OCP

LEB

blank

Iss

2.5 V

burst
detect

  Block diagram.

V

CC

1

supply voltage

GND

2

ground

CTRL

3

control input

DEM

4

input from auxiliary winding for
demagnetization timing, OVP and OPP

I

sense

5

programmable current sense input

DRIVER

6

gate driver output

HVS

7

high voltage safety spacer, not
connected

DRAIN

8

drain of external MOS switch, input for
start-up current and valley sensing

handbook, halfpage

MGU231

1

2

3

4

VCC

GND

CTRL

DEM

DRAIN

HVS

DRIVER

Isense

8

7

6

5

  Pin configuration.

1

2

3

4

5

6

7

8

9

V

CC

Output

            GND

Output

Standby

Input

GND

N.C.

V

olume

Pin No.

Description

1

Vcc

2

Ch Output (+)

3

GND

4

Ch Output (-)

5

Standby

6

Ch Input

7

GND (Input)

8

N.C

9

Volume

Circuit Function Block Diagram

Pin Descriptions

Note: Do not apply voltage or current to NC pin from outside

Pin No.

Pin Name

1

Inverting Input

2

Power Supply

3

Pump-up Output

4

GND

5

Vertical Output

6

Vertical Output Power Supply

7

Non-inverting Input

Pin Descriptions

Non-inverting Input

Output Vcc

Output

GND

Pump Up Out

Vcc

Inverting Input

1

2

3

4

5

6

7

Pump Up

Thermal Protection

Amp

+

-

Circuit Function Block Diagram

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.

T

A

Ambient Operating Temperature

–

0

70

°C

T

S

Storage Temperature

–

−40

125

°C

V

SUP1

First Supply Voltage

AHVSUP

−0.3

9.0

V

V

SUP2

Second Supply Voltage

DVSUP

−0.3

6.0

V

V

SUP3

Third Supply Voltage

AVSUP

−0.3

6.0

V

dV

SUP23

Voltage between AVSUP 
and DVSUP

AVSUP,
DVSUP

−0.5

0.5

V

P

TOT

Package Power Dissipation
PSDIP64
PSDIP52
PQFP80
PLQFP64
PMQFP44

AHVSUP,
DVSUP, 
AVSUP

1300
1200
1000

960
960

mW
mW
mW
mW
mW

V

Idig

Input Voltage, all Digital Inputs

−0.3

V

SUP2

+0.3

V

I

Idig

Input Current, all Digital Pins

–

−20

+20

mA

1)

V

Iana

Input Voltage, all Analog Inputs

SCn_IN_s,

2)

MONO_IN

−0.3

V

SUP1

+0.3

V

I

Iana

Input Current, all Analog Inputs

SCn_IN_s,

2)

MONO_IN

−5

+5

mA

1)

I

Oana

Output Current, all SCART Outputs

SC1_OUT_s

2)

3)

, 

4)

3)

, 

4)

I

Oana

Output Current, all Analog Outputs 
except SCART Outputs

DACM_s

2)

3)

3)

I

Cana

Output Current, other pins 
connected to capacitors

CAPL_M,
AGNDC

3)

3)

1)

positive value means current flowing into the circuit

2)

“n” means “1” or “2”,     “s” means “L” or “R”

3)

The Analog Outputs are short-circuit proof with respect to First Supply Voltage and Ground.

4)

Total chip power dissipation must not exceed absolute maximum rating.

PMQFP44 package

CAPL_M

AHVSS

AGNDC

SC2_IN_L

SC2_IN_R

ASG

SC1_IN_L

SC1_IN_R

VREFTOP

MONO_IN

AVSS

RESETQ

I2S_DA_IN2

DVSS

DVSUP

ADR_CL

I2S_DA_IN1

I2S_DA_OUT

I2S_WS

I2S_CL

I2C_DA

I2C_CL

NC

SC1_OUT_L

SC1_OUT_R

VREF1

NC

AHVSUP

DACM_L

DACM_R

VREF2

NC

NC

ANA_IN1

+

ANA_IN

−

TESTEN

XTAL_IN

XTAL_OUT

AVSUP

TP

D_CTR_I/O1

D_CTR_I/O0

ADR_SEL

STANDBYQ

34

35

36

37

38

39

40

41

42

43

44

22

21

20

19

18

17

16

15

14

13

12

1

2

3

4

5

6

7

8

9

10 11

33 32 31 30 29 28 27 26 25 24 23

Simplified functional block diagram of MSP 34x5G

Sour

ce 

Select

Loud-

SCART1

SCART1

SCART2

MONO

De-

modulator

speaker

Sound

Processing

DAC

ADC

Loud-

DAC

ADC

Sound IF1

speaker

I

2

S

I

2

S1

I

2

S2

Pre-

processing

Prescale

Prescale

SCART

DSP

Input

Select

SCART

Output

Select