Sharp MX-PNX1A (serv.man2) Service Manual ▷ View online
MX-FNX1/MX-PNX1 ELECTRICAL SECTION 10 – 7
d. Flapper solenoid (FINRPS), belt separation solenoid (FBRS), paper surface detection solenoid (FSLS), paddle one-rotation
solenoid (FPDS) drive circuit
solenoid (FPDS) drive circuit
This circuit controls attachment and release of the flapper solenoid (FINRPS), the belt separation solenoid (FBRS), the paper surface detection
solenoid (FSLS), and the paddle one-rotation solenoid (FPDS).
The CPU (IC10-24, 26) outputs the drive signal of the flapper solenoid (FINRPS) and the paddle one-rotation solenoid (FPDS) to turn ON Q23
and Q20 to attach the solenoid.
The CPU (IC10-27,28) outputs the drive signal of the belt separation solenoid (FBRS) and paper surface detection solenoid (FSLS) to turn on
Q19 and Q22 to attach the solenoid.
The drive signal of the flapper solenoid (FINRPS) and the paper surface detection solenoid is a PWM signal. After completion of attachment,
the flapper solenoid (FINRPS) duty is 20%. Paper surface detection solenoid (FSLS): Duty is reduced to 50% and the solenoid temperature
rise is reduced to keep attachment.
solenoid (FSLS), and the paddle one-rotation solenoid (FPDS).
The CPU (IC10-24, 26) outputs the drive signal of the flapper solenoid (FINRPS) and the paddle one-rotation solenoid (FPDS) to turn ON Q23
and Q20 to attach the solenoid.
The CPU (IC10-27,28) outputs the drive signal of the belt separation solenoid (FBRS) and paper surface detection solenoid (FSLS) to turn on
Q19 and Q22 to attach the solenoid.
The drive signal of the flapper solenoid (FINRPS) and the paper surface detection solenoid is a PWM signal. After completion of attachment,
the flapper solenoid (FINRPS) duty is 20%. Paper surface detection solenoid (FSLS): Duty is reduced to 50% and the solenoid temperature
rise is reduced to keep attachment.
e. Reset circuit
This circuit generates the reset signal and supplies it to the CPU
when the power is turned ON and when the power voltage fall is
detected.
IC13-6pin (OUT) is normally at HIGH level after turning ON the
power. When, however, +5V power voltage falls to 4.05V or less
because of power OFF or any other reasons, IC13-6pin is driven to
LOW level, resetting the CPU.
when the power is turned ON and when the power voltage fall is
detected.
IC13-6pin (OUT) is normally at HIGH level after turning ON the
power. When, however, +5V power voltage falls to 4.05V or less
because of power OFF or any other reasons, IC13-6pin is driven to
LOW level, resetting the CPU.
f. EEPROM circuit
This circuit is composed of EEPROM which stores data and the
peripheral circuit.
IC12 is a memory which stores the adjustment values of the inner
punch transmission-type optical sensor and the alignment plate
position, and it sends/receives data to/from the CPU through the 4-
wire type serial interface. The data stored once are kept undeleted
even when the power is turned OFF.
IC12-1pin (CS) is the chip select pin and is at HIGH level when
data are sent or received.
IC12-2pin (SK) is the serial clock pin. Serial data are inputted to
this pin and sent in synchronization with the clock.
IC12-3pin (DI) is the serial data input pin, and IC12-4pin (DO) is the
serial data output pin.
peripheral circuit.
IC12 is a memory which stores the adjustment values of the inner
punch transmission-type optical sensor and the alignment plate
position, and it sends/receives data to/from the CPU through the 4-
wire type serial interface. The data stored once are kept undeleted
even when the power is turned OFF.
IC12-1pin (CS) is the chip select pin and is at HIGH level when
data are sent or received.
IC12-2pin (SK) is the serial clock pin. Serial data are inputted to
this pin and sent in synchronization with the clock.
IC12-3pin (DI) is the serial data input pin, and IC12-4pin (DO) is the
serial data output pin.
Flapper solenoid
(FINRPS)
(FINRPS)
Paddle one-rotation
solenoid (FPDS)
solenoid (FPDS)
Paper surface detection
solenoid (FSLS)
solenoid (FSLS)
Belt separation solenoid
(FBRS)
(FBRS)
Not
installed
installed
MX-FNX1/MX-PNX1 ELECTRICAL SECTION 10 – 8
g. Rush current limit circuit
This circuit limits a rush current flowing through the current-regen-
erating capacitor in the motor drive system to a certain level. It is
composed of the posister (PTH2) which limits a current and the
FET (Q3) which flows a current in the steady state.
From when the front cover switch (FDSW) is closed to when the
cathode voltage of ZD1 reaches the zener voltage by the time con-
stant of R42 and C14, the base current is not supplied to Q1, turn-
ing OFF Q1 and Q3. During this period, a current flows through
PTH2 to charge the current regenerating capacitor.
After the current regenerating capacitor is fully charged, when the
cathode voltage of ZD1 exceeds the zener voltage by the time con-
stant of R42 and C14, the base current is supplied to Q1 to turn ON
Q1 and Q3. The current flowing through PTH2 flows through Q3,
releasing the current limit operation.
The circuit composed of PTH1 and D1 immediately removes elec-
tric charges accumulated in C14 when the front cover switch
(FDSW) is opened. This circuit allows the rush current limit opera-
tion for instantaneous open/close of the cover.
erating capacitor in the motor drive system to a certain level. It is
composed of the posister (PTH2) which limits a current and the
FET (Q3) which flows a current in the steady state.
From when the front cover switch (FDSW) is closed to when the
cathode voltage of ZD1 reaches the zener voltage by the time con-
stant of R42 and C14, the base current is not supplied to Q1, turn-
ing OFF Q1 and Q3. During this period, a current flows through
PTH2 to charge the current regenerating capacitor.
After the current regenerating capacitor is fully charged, when the
cathode voltage of ZD1 exceeds the zener voltage by the time con-
stant of R42 and C14, the base current is supplied to Q1 to turn ON
Q1 and Q3. The current flowing through PTH2 flows through Q3,
releasing the current limit operation.
The circuit composed of PTH1 and D1 immediately removes elec-
tric charges accumulated in C14 when the front cover switch
(FDSW) is opened. This circuit allows the rush current limit opera-
tion for instantaneous open/close of the cover.
B. MX-PNX1A/B/C/D
(1) General
This circuit controls the punch function of paper discharged from
the main unit.
It is composed of circuits which process signals from sensors and
the inner finisher and the circuit which drives the motors.
the main unit.
It is composed of circuits which process signals from sensors and
the inner finisher and the circuit which drives the motors.
(2) Circuit descriptions
a. Sensor input circuit
1)
Full sensor (FPDD)
The full sensor (FPDD) employs the photo interrupter in which
the light emitting diode and the photo transistor are integrated.
The full state is detected by interruption of lights with the light-
shielding plate. By use of Q8, the logic when the connector is
disconnected is made the same as when light is emitted to the
sensor (full).
Signals are inputted through the noise filter of R10 and C2 to
the multiplexer (IC9-4pin).
The logic of a signal inputted to the CPU on the inner finisher
circuit is fixed to H when the punch dust container is full.
R2 is the current limit resistor of the light emitting diode, and
R6 is the load resistor of the sensor.
The full sensor (FPDD) employs the photo interrupter in which
the light emitting diode and the photo transistor are integrated.
The full state is detected by interruption of lights with the light-
shielding plate. By use of Q8, the logic when the connector is
disconnected is made the same as when light is emitted to the
sensor (full).
Signals are inputted through the noise filter of R10 and C2 to
the multiplexer (IC9-4pin).
The logic of a signal inputted to the CPU on the inner finisher
circuit is fixed to H when the punch dust container is full.
R2 is the current limit resistor of the light emitting diode, and
R6 is the load resistor of the sensor.
2)
Punch position sensor (FPHPD)
The punch position sensor (FPHPD) employs the photo inter-
rupter in which the light emitting diode and the photo transistor
are integrated.
The full state is detected by interruption of lights with the light-
shielding plate. By use of Q9, the logic when the connector is
disconnected is made the same as when light is emitted to the
sensor (when punching).
Signals are inputted through the noise filter of RA11.2 and C55
in the inner finisher circuit to the CPU (IC10-87pin).
The logic of a signal inputted to the CPU is fixed to H at the
home position, and L when punching.
R1 is the current limit resistor of the light emitting diode, and
R97 (in the inner finisher circuit) is the load resistor of the sen-
sor.
The punch position sensor (FPHPD) employs the photo inter-
rupter in which the light emitting diode and the photo transistor
are integrated.
The full state is detected by interruption of lights with the light-
shielding plate. By use of Q9, the logic when the connector is
disconnected is made the same as when light is emitted to the
sensor (when punching).
Signals are inputted through the noise filter of RA11.2 and C55
in the inner finisher circuit to the CPU (IC10-87pin).
The logic of a signal inputted to the CPU is fixed to H at the
home position, and L when punching.
R1 is the current limit resistor of the light emitting diode, and
R97 (in the inner finisher circuit) is the load resistor of the sen-
sor.
3)
Rear position sensor (FPRPD)
The rear position sensor (FPRPD) employs the photo inter-
rupter in which the light emitting diode and the photo transistor
are integrated.
The rear position is detected by interruption of lights with the
light-shielding plate.
Signals are inputted through the noise filter of RA11.3 and C56
in the inner finisher circuit to the CPU (IC10-16pin). The logic
of a signal inputted to the CPU is H when light is shielded and
L when light is emitted to the sensor.
R4 is the current limit resistor of the light emitting diode, and
R98 (in the inner finisher circuit) is the load resistor of the sen-
sor.
The rear position sensor (FPRPD) employs the photo inter-
rupter in which the light emitting diode and the photo transistor
are integrated.
The rear position is detected by interruption of lights with the
light-shielding plate.
Signals are inputted through the noise filter of RA11.3 and C56
in the inner finisher circuit to the CPU (IC10-16pin). The logic
of a signal inputted to the CPU is H when light is shielded and
L when light is emitted to the sensor.
R4 is the current limit resistor of the light emitting diode, and
R98 (in the inner finisher circuit) is the load resistor of the sen-
sor.
4)
Horizontal shift HP sensor (FPSHPD)
The horizontal shift HP sensor (FPSHPD) employs the photo
interrupter in which the light emitting diode and the photo tran-
sistor are integrated.
The home position is detected by interruption of lights with the
light-shielding plate.
Signals are inputted through the noise filter of RA11.4 and C57
in the inner finisher circuit to the CPU (IC10-17pin). The logic
of a signal inputted to the CPU is H when light is shielded and
L when light is emitted to the sensor.
R58 is the current limit resistor of the light emitting diode, and
R99 (in the inner finisher circuit) is the load resistor of the sen-
sor.
The horizontal shift HP sensor (FPSHPD) employs the photo
interrupter in which the light emitting diode and the photo tran-
sistor are integrated.
The home position is detected by interruption of lights with the
light-shielding plate.
Signals are inputted through the noise filter of RA11.4 and C57
in the inner finisher circuit to the CPU (IC10-17pin). The logic
of a signal inputted to the CPU is H when light is shielded and
L when light is emitted to the sensor.
R58 is the current limit resistor of the light emitting diode, and
R99 (in the inner finisher circuit) is the load resistor of the sen-
sor.
Main unit
Front cover switch (FDSW)
Full sensor (FPDD)
Punch position sensor (FPHPD)
Rear position sensor (FPRPD)
Horizontal shift HP sensor (FPSHPD)
MX-FNX1/MX-PNX1 ELECTRICAL SECTION 10 – 9
5)
Paper rear edge sensor (FPPEND) and paper horizontal resist sensor (FPPD1 – 6)
This circuit is a transmission-type optical sensor circuit using the LED PWB and the photo transistor PWB.
Paper is detected when the light path is interrupted by paper passing between the photo transistor PWB and the LED PWB.
The light emitting circuit of LED1 – 6 is composed of the CPU (IC10) on the inner finisher circuit, the DA converter (IC11), the multiplexer
(IC7) on the above punch PWB, the operation amplifier (IC10, 11), and the transistors (Q7, 9, 10, 11). The analog signal (DA_COM) and
the select signals (A1, B1, C1) are inputted to the multiplexer (IC7-3, 9, 10, 11pin) to select the light emitting circuit. The DA adjustment
value outputted from the multiplexer (IC7-1, 5, 12, 13, 14, 15pin) is used to adjust the current flowing through the LED via the operation
amplifier and the transistor. R30, 3, 42, 43, 44, 45 are the LED current limit resistors.
The light emitting circuit of YK_LED is composed of the CPU (IC10) on the inner finisher circuit, the DA converter (IC11), the operation
amplifier (IC11) on the above punch PWB, and the transistor (Q7). The analog signal (YK_LED_DA : DA adjustment value) adjusts the cur-
rent flowing through the LED via the operation amplifier and the transistor. R63 is the LED current limit resistor.
The light receiving circuit of B5R, 16K-R, A4R, B4R, LTR-Y, A3 is composed of the CPU (IC10) on the inner finisher circuit, the comparator
(IC9), the multiplexer (IC9) on the above punch PWB, and the operation amplifier (IC12, 13).
The select signal (A1, B1, C1) inputted to the multiplexer (IC9-9, 10, 11pin) is used to select the light receiving circuit. The sensor output is
inputted to the multiplexer (IC9-1, 5, 12, 13, 14, 15pin) through the operation amplifier, and the analog signal (AN_COM1) is inputted to the
CPU through the comparator (IC9). R46, 53, 54, 55, 56, and 57 are the load resistors of the photo transistor.
The light receiving circuit of YK_PTR_AN is composed of the CPU (IC10), the comparator (IC9), and the operation amplifier (IC11) on the
above punch PWB. The analog signal (YK_PTR_AN) is inputted from the comparator (IC9) through the operation amplifier (IC11) to the
CPU. R65 is the load resistor of the photo transistor. The logic of the signal inputted to the CPU is L when paper is provided.
The threshold voltage of the comparator on the inner finisher circuit is 5V divided with R100 and R101.
This circuit is a transmission-type optical sensor circuit using the LED PWB and the photo transistor PWB.
Paper is detected when the light path is interrupted by paper passing between the photo transistor PWB and the LED PWB.
The light emitting circuit of LED1 – 6 is composed of the CPU (IC10) on the inner finisher circuit, the DA converter (IC11), the multiplexer
(IC7) on the above punch PWB, the operation amplifier (IC10, 11), and the transistors (Q7, 9, 10, 11). The analog signal (DA_COM) and
the select signals (A1, B1, C1) are inputted to the multiplexer (IC7-3, 9, 10, 11pin) to select the light emitting circuit. The DA adjustment
value outputted from the multiplexer (IC7-1, 5, 12, 13, 14, 15pin) is used to adjust the current flowing through the LED via the operation
amplifier and the transistor. R30, 3, 42, 43, 44, 45 are the LED current limit resistors.
The light emitting circuit of YK_LED is composed of the CPU (IC10) on the inner finisher circuit, the DA converter (IC11), the operation
amplifier (IC11) on the above punch PWB, and the transistor (Q7). The analog signal (YK_LED_DA : DA adjustment value) adjusts the cur-
rent flowing through the LED via the operation amplifier and the transistor. R63 is the LED current limit resistor.
The light receiving circuit of B5R, 16K-R, A4R, B4R, LTR-Y, A3 is composed of the CPU (IC10) on the inner finisher circuit, the comparator
(IC9), the multiplexer (IC9) on the above punch PWB, and the operation amplifier (IC12, 13).
The select signal (A1, B1, C1) inputted to the multiplexer (IC9-9, 10, 11pin) is used to select the light receiving circuit. The sensor output is
inputted to the multiplexer (IC9-1, 5, 12, 13, 14, 15pin) through the operation amplifier, and the analog signal (AN_COM1) is inputted to the
CPU through the comparator (IC9). R46, 53, 54, 55, 56, and 57 are the load resistors of the photo transistor.
The light receiving circuit of YK_PTR_AN is composed of the CPU (IC10), the comparator (IC9), and the operation amplifier (IC11) on the
above punch PWB. The analog signal (YK_PTR_AN) is inputted from the comparator (IC9) through the operation amplifier (IC11) to the
CPU. R65 is the load resistor of the photo transistor. The logic of the signal inputted to the CPU is L when paper is provided.
The threshold voltage of the comparator on the inner finisher circuit is 5V divided with R100 and R101.
MX-FNX1/MX-PNX1 ELECTRICAL SECTION 10 – 10
b. Motor drive circuit
1)
1)
Punch horizontal resist motor (FPSM) drive circuit
This circuit controls the punch horizontal resist motor (FPSM) rotation/stop, the rotating direction, and the motor current, and is composed
of the CPU (IC10) on the finisher circuit, the DA converter (IC11), and the constant-current chopper type driver IC (IC2) in the above circuit.
The stepping motor drive excitement pattern signal (YI_MOT_PA, PB, EA, EB) outputted from the CPU (IC10-83, 84, 85, 86pin) is used to
control the motor rotating speed and the rotating direction.
The analog signal (YI_MOT_REF) outputted from the DA converter (IC11-6pin) is divided to a fixed voltage with R17 and R18. This divided
voltage is inputted to IC2-3, 4pin to set the motor current value. The logic of the standby signal (MOT_STY) outputted from the DA con-
verter (IC11-7pin) is H when the motor can be operated.
of the CPU (IC10) on the finisher circuit, the DA converter (IC11), and the constant-current chopper type driver IC (IC2) in the above circuit.
The stepping motor drive excitement pattern signal (YI_MOT_PA, PB, EA, EB) outputted from the CPU (IC10-83, 84, 85, 86pin) is used to
control the motor rotating speed and the rotating direction.
The analog signal (YI_MOT_REF) outputted from the DA converter (IC11-6pin) is divided to a fixed voltage with R17 and R18. This divided
voltage is inputted to IC2-3, 4pin to set the motor current value. The logic of the standby signal (MOT_STY) outputted from the DA con-
verter (IC11-7pin) is H when the motor can be operated.
2)
Punch motor (FPNM) drive circuit
This circuit controls the punch motor (FPNM) rotation/stop, and the rotating direction, and is composed of the CPU (IC10) on the finisher
circuit and the FET (Q1, 2, 3, 4). The CPU (IC10-98,99,100pin) outputs the punch motor (FPNM) drive forward rotation signal, the reverse
rotation signal, and the brake signal to control the DC motor.
circuit and the FET (Q1, 2, 3, 4). The CPU (IC10-98,99,100pin) outputs the punch motor (FPNM) drive forward rotation signal, the reverse
rotation signal, and the brake signal to control the DC motor.
Punch horizontal resist motor
(FPSM)
(FPSM)
Not installed
Punch motor (FPNM)
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