DOWNLOAD Sharp MX-6500N / MX-7500N (serv.man30) Service Manual ↓ Size: 10.27 MB | Pages: 127 in PDF or view online for FREE

Model
MX-6500N MX-7500N (serv.man30)
Pages
127
Size
10.27 MB
Type
PDF
Document
Service Manual
Brand
Device
Copying Equipment / Circuit Diagram
File
mx-6500n-mx-7500n-sm30.pdf
Date

Sharp MX-6500N / MX-7500N (serv.man30) Service Manual ▷ View online

MX-7500N  BLOCK DIAGRAM / ブ ロ ッ ク図  1 –  8
LSU CNT PWB (2/2)
LSU_ASIC
CHIP-2
SCN
Mother
LD
LSU_ASIC
CHIP-3
ID[1:0]
I2C 
ROM
I2C BUS
Hard reset
SCK
RSV_DAT
TRANS_RST
TRANS_DAT
Clock synchronization serial communication
JOBEND_INT_C
System CK
HSYNC/ECLK
Motor control
Polygon 
control
Fan control
LD control
LD control
(APC etc.)
BD
nVSYNC_C
DT_C1+-
2
DT_C2+-
2
DT_C3+-
2
DT_C4+-
2
LSU_ASIC
CHIP-4
Main scanning, 
Sub scanning 
timing control
PCU I/F
Register etc...
ID[1:1]
I2C 
ROM
I2C BUS
Hard reset
SCK
RSV_DAT
TRANS_RST
TRANS_DAT
Clock synchronization serial communication
JOBEND_INT_K
Serial 
D/A I/F
LD control
LD control
(APC etc.)
8
DT_K1+-
2
DT_K2+-
2
DT_K3+-
2
DT_K4+-
2
Channel A: K1 circuit
Channel B: K2 circuit
Channel C: K3 circuit
Channel D: K4 circuit
PGM_CK
PGM_START
(PGM_BREAK)
CLK_C_EN
CLK_M_EN
CLK_A_EN
Motor control
Polygon 
control
Fan control
PGM_LOCK
Polygon 
motor
LSU
FAN
FAN_PWM
FANSTABLE
O.C.
O.C.
O.C.
3
S/S
ECLK
HSYNC
LVDS/Dr
iv
er
ECLK
HSYNC
nVSYNC_K
Image transfer CK
HSYNC
ECLK
HSYNC
VSYNC
ASIC
to CHIP-1/2/3
SYSCLK
Oscillator
(System CK)
ASIC
from CHIP-1/2/3
nVSYNC_Y/C/M
4
FPD-LINK/Reciv
er
ASIC
to CHIP-1/2/3
VIDEOIF_ACT
O.C.
nLDERRY/M/C/K
ASIC
to CHIP-1/2/3
BD
PCU I/F
Register etc...
Channel A: C1 circuit
Channel B: C2 circuit
Channel C: C3 circuit
Channel D: C4 circuit
FPD-LINK/Reciv
er
Print trigger chain
Print trigger chain
BD
OSCCLK_C
OSCCLK_M
OSCCLK_A
4
MFPC
Or
EFI
Serial 
D/A I/F
3
nP2_L_AK1
nP1_L_AK1
nP0_L_AK1
nSEL_SH
nINT STC/K
4
SD_CLK
4
MSET_K/C
GAIN_FIX
2
P4_C_AK1(ENB)
P4_C_AK2(ENB)
2
P4_K_AK1(ENB)
P4_K_AK2(ENB)
P3_K_AK1
nP3_WAIT_AK1
nn#P0_AK1
#P0_1_AK1
nn#P2_AK1
nn#P1_AK1
SD_CLK
circuit
SDCLK_ENB
SDCLK_ENB
O.C.
8
35:5
35:5
#P0_2_AK1
SEL_ADJ_Y/M/C/K
P3_K_AK2
nP3_WAIT_AK2
nSEL_ADJ_K
3
nP2_L_AK2
nP1_L_AK2
nP0_L_AK2
nSEL_SH
nn#P0_AK2
#P0_1_AK2
nn#P2_AK2
nn#P1_AK2
#P0_2_AK2
P3_C_AK1
P3_WAIT_AK1
P3_C_AK2
P3_WAIT_AK2
nSEL_ADJ_C
P3_ADJ
P3_ADJ
#P0_3_AK2
O.C.
Main scanning, 
Sub scanning 
timing control
MX-7500N  BLOCK DIAGRAM / ブ ロ ッ ク図  1 –  9
7. SERIAL COMMUNICATION / シ リ アル通信
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MX-7500N  CIRCUIT DIAGRAM AND PARTS LAYOUT / 回路図 と 部品配置図  2 –  1
[2] CIRCUIT DIAGRAM AND PARTS LAYOUT / 回路図 と 部品配置図
1. MFP CONTROL PWB / MFP コ ン ト ロール PWB
A. CIRCUIT DIAGRAM / 回路図
5
5
4
4
3
3
D
C
B
A
‧⁈‾
‧⁈⁁
ARM9_OFF_N
DGND
5V0_FAX_IN
DGND
DGND
DGND
5V0_FAX_IN
5V_IN
5V0_FAX_IN
5V_IN
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
5V0_FAX_IN
5V_IN
DGND
DGND
R1_3R3V_ON
DGND
5V0_FAX_IN
DGND
5V0_FAX_IN
DGND
DGND
DGND
5V_IN
DGND
RS_3R3V_ECO
R1B_GPO_SELFRST
{11}
nREUS_
CP997
CP997
R612
47KJ
R612
47KJ
CP1050
CP1050
SW 2
D_SKQMBAE010
SW 2
D_SKQMBAE010
R537
2.2KJ
R537
2.2KJ
R1690
1KJ
R1690
1KJ
R1168
47KJ
R1168
47KJ
CP1046
CP1046
R611
X_0J
R611
X_0J
R580
47KJ
R580
47KJ
R1171
10KJ
R1171
10KJ
CP1011
CP1011
C375
0.1uF(B:10V)
C375
0.1uF(B:10V)
C364
1000pF(B:50V)
C364
1000pF(B:50V)
R578
X_0J
R578
X_0J
CP1009
CP1009
CP1051
CP1051
C367
1000pF(B:50V)
C367
1000pF(B:50V)
CP996
CP996
R1169
1KJ
R1169
1KJ
C1324
1uF(1608:B:10V)
C1324
1uF(1608:B:10V)
C1281
1uF(1608:B:10V)
C1281
1uF(1608:B:10V)
C363
0.1uF(B:10V)
C363
0.1uF(B:10V)
R583
1KJ
R583
1KJ
R584
47KJ
R584
47KJ
10K
47K
Q34
DTC014YUB
10K
47K
Q34
DTC014YUB
E
B
C
D27
D_LTST-C190KGKT
D27
D_LTST-C190KGKT
A
K
R1170
47KJ
R1170
47KJ
IC55
74LVC1G07GW
IC55
74LVC1G07GW
NC
1
A
2
GND
3
Y
4
VCC
5
C1321
X_0.1uF(1608:B)
C1321
X_0.1uF(1608:B)
C376
1000pF(B:50V)
C376
1000pF(B:50V)
IC86
PST8435UL
IC86
PST8435UL
GND
1
VDD
2
CT
3
VOUT
4
C1322
1000pF(B:50V)
C1322
1000pF(B:50V)
D26
LTST-C190KGKT
D26
LTST-C190KGKT
A
K
IC51
74LVC1G07GW
IC51
74LVC1G07GW
NC
1
A
2
GND
3
Y
4
VCC
5
CP1048
CP1048
IC84
PST8435UL
IC84
PST8435UL
GND
1
VDD
2
CT
3
VOUT
4
CP1018
CP1018
C1323
47000pF(B:10V)
C1323
47000pF(B:10V)
CP1019
CP1019
C1280
1uF(1608:B:10V)
C1280
1uF(1608:B:10V)
IC83
BD45382G-TR
IC83
BD45382G-TR
ER
1
SUB
2
GND
3
VOUT
4
VDD
5
CP1047
CP1047
D
S
G
1
2
3
Q32
2SK3018
D
S
G
1
2
3
Q32
2SK3018
R538
D_2.2KJ
R538
D_2.2KJ
D
S
G
1
2
3
Q33
2SK3018
D
S
G
1
2
3
Q33
2SK3018
MX-7500N  CIRCUIT DIAGRAM AND PARTS LAYOUT / 回路図 と 部品配置図  2 –  2
2
2
1
1
D
C
B
A
ARM9_OFF_N
ARM11_OFF_N
DGND
DGND
5V0_FAX_IN
_FAX_IN
DGND
5V0_FAX_IN
DGND
DGND
DGND
DGND
5V_IN
5V_IN
5V_IN
RS_3R3V_ECO
IN
DGND
ARM9_OFF_N
{10,42}
nREUS_SYSRST
{19}
R1_CPLD_RST_N
{13}
ARM11_OFF_N
{4,5,7}
1
59
1
59
1
59
CP1049
CP1049
R582
47KJ
R582
47KJ
CP1014
CP1014
R1172
100KJ
R1172
100KJ
R1160
47KJ
R1160
47KJ
CP1334
CP1334
C366
1uF(1608:B:10V)
C366
1uF(1608:B:10V)
CP1020
CP1020
D
S
G
1
2
3
Q29
2SK3018
D
S
G
1
2
3
Q29
2SK3018
CP1015
CP1015
CP1017
CP1017
R1689
1KJ
R1689
1KJ
IC85
74LVC1G07GW
IC85
74LVC1G07GW
NC
1
A
2
GND
3
Y
4
VCC
5
R579
4.7KJ
R579
4.7KJ
IC52
BD45371G-TR
IC52
BD45371G-TR
ER
1
SUB
2
GND
3
VOUT
4
VDD
5
CP1016
CP1016
C1320
0.1uF(B:10V)
C1320
0.1uF(B:10V)
R581
1KJ
R581
1KJ
C365
1000pF(B:50V)
C365
1000pF(B:50V)
R610
4.7KJ
R610
4.7KJ
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