Sharp MX-6500N / MX-7500N (serv.man30) Service Manual ▷ View online
MX-7500N BLOCK DIAGRAM / ブ ロ ッ ク図 1 – 6
5. MFP CONTROL PWB / MFP コ ン ト ロール PWB
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MX-7500N BLOCK DIAGRAM / ブ ロ ッ ク図 1 – 7
6. LSU CNT PWB
LSU CNT PWB (1/2)
LSU_ASIC
CHIP-2
LSU_ASIC
CHIP-1
SCN
Mother
Thermistor
Motor control
PCU
8
PCU I/F
Register
etc...
SCK
RSV_DAT
TRANS_RST
TRANS_DAT
JOBEND_INT_Y
Clock synchronization serial communication
Thermistor output
PCU_TRG
Print trigger input
AMP
Reset IC
Reset input
Hard reset
35:5
ID[0:0]
ID[0:1]
I2C
ROM
I2C
ROM
I2C BUS
ASIC
to CHIP-2/3/4
Hard reset
SCK
RSV_DAT
TRANS_RST
TRANS_DAT
Clock synchronization serial communication
JOBEND_INT_M
System CK
HSYNC/ECLK
35:5
Print trigger chain
LD
Polygon
control
control
Fan
control
I2C BUS
DT_Y1+-
3
2
DT_Y2+-
2
DT_Y3+-
2
DT_Y4+-
2
FPD-LINK/Reciver
Motor control
Polygon
control
Fan
control
Serial
D/A I/F
LD control
LD control
(APC etc.)
(APC etc.)
Oscillator
(CK for 330mm/s)
Oscillator
(CK for 300 or 360mm/s)
Oscillator
(CK for 220mm/s)
OSCCLK_C
OSCCLK_M
OSCCLK_A
CLK_C_EN
CLK_M_EN
CLK_A_EN
TH
nVSYNC_M
8
DT_M1+-
2
DT_M2+-
2
DT_M3+-
2
DT_M4+-
2
ASIC
to CHIP-2/3/4
ASIC
from CHIP-2/3/4
LSU_ASIC
CHIP-3
BD
PCU I/F
Register etc...
Channel A: M1 circuit
Channel B: M2 circuit
Channel C: M3 circuit
Channel D: M4 circuit
Channel A: Y1 circuit
Channel B: Y2 circuit
Channel C: Y3 circuit
Channel D: Y4 circuit
Main scanning,
Sub scanning
timing control
System CK
HSYNC/ECLK
nVSYNC_Y
Serial
D/A I/F
LD control
LD control
(APC etc.)
(APC etc.)
Print trigger chain
BD
MFPC
Or
EFI
Thermistor
2
Thermistor output
AMP
TH2
4
MSET_M/Y
4
2
P4_Y_AK1(ENB)
P4_Y_AK2(ENB)
P4_Y_AK2(ENB)
MicroWire BUS
SCLK/TXD/RXD
3
Chip select(EEP-ROM)
CS EEP-ROM K/C/M/Y
8
Chip setect(LDD)
CS K/C/M/Y
8
2
P4_M_AK1(ENB)
P4_M_AK2(ENB)
P4_M_AK2(ENB)
JOBEND_INT
JOBEND_INT_M
JOBEND_INT_C
JOBEND_INT_K
nJOBEND_INT_Y
nJOBEND_INT_M
nJOBEND_INT_C
nJOBEND_INT_K
nINT STM/Y
P3_M_AK1
P3_WAIT_AK1
P3_M_AK2
P3_WAIT_AK2
nSEL_ADJ_M
P3_ADJ
P3_Y_AK1
P3_WAIT_AK1
P3_Y_AK2
P3_WAIT_AK2
nSEL_ADJ_Y
P3_ADJ
Main scanning,
Sub scanning
timing control
FPD-LINK/Reciv
er
MX-7500N BLOCK DIAGRAM / ブ ロ ッ ク図 1 – 8
LSU CNT PWB (2/2)
LSU_ASIC
CHIP-2
SCN
Mother
LD
LSU_ASIC
CHIP-3
ID[1:0]
I2C
ROM
I2C BUS
Hard reset
SCK
RSV_DAT
TRANS_RST
TRANS_DAT
Clock synchronization serial communication
JOBEND_INT_C
System CK
HSYNC/ECLK
Motor control
Polygon
control
Fan control
LD control
LD control
(APC etc.)
(APC etc.)
BD
nVSYNC_C
DT_C1+-
2
DT_C2+-
2
DT_C3+-
2
DT_C4+-
2
LSU_ASIC
CHIP-4
Main scanning,
Sub scanning
timing control
PCU I/F
Register etc...
ID[1:1]
I2C
ROM
I2C BUS
Hard reset
SCK
RSV_DAT
TRANS_RST
TRANS_DAT
Clock synchronization serial communication
JOBEND_INT_K
Serial
D/A I/F
LD control
LD control
(APC etc.)
(APC etc.)
8
DT_K1+-
2
DT_K2+-
2
DT_K3+-
2
DT_K4+-
2
Channel A: K1 circuit
Channel B: K2 circuit
Channel C: K3 circuit
Channel D: K4 circuit
PGM_CK
PGM_START
(PGM_BREAK)
CLK_C_EN
CLK_M_EN
CLK_A_EN
Motor control
Polygon
control
Fan control
PGM_LOCK
Polygon
motor
LSU
FAN
FAN
FAN_PWM
FANSTABLE
O.C.
O.C.
O.C.
3
S/S
ECLK
HSYNC
LVDS/Dr
iv
er
ECLK
HSYNC
nVSYNC_K
Image transfer CK
HSYNC
ECLK
HSYNC
VSYNC
ASIC
to CHIP-1/2/3
SYSCLK
Oscillator
(System CK)
ASIC
from CHIP-1/2/3
nVSYNC_Y/C/M
4
FPD-LINK/Reciv
er
ASIC
to CHIP-1/2/3
VIDEOIF_ACT
O.C.
nLDERRY/M/C/K
ASIC
to CHIP-1/2/3
BD
PCU I/F
Register etc...
Channel A: C1 circuit
Channel B: C2 circuit
Channel C: C3 circuit
Channel D: C4 circuit
FPD-LINK/Reciv
er
Print trigger chain
Print trigger chain
BD
OSCCLK_C
OSCCLK_M
OSCCLK_A
4
MFPC
Or
EFI
Serial
D/A I/F
3
nP2_L_AK1
nP1_L_AK1
nP0_L_AK1
nP1_L_AK1
nP0_L_AK1
nSEL_SH
nINT STC/K
4
SD_CLK
4
MSET_K/C
GAIN_FIX
2
P4_C_AK1(ENB)
P4_C_AK2(ENB)
P4_C_AK2(ENB)
2
P4_K_AK1(ENB)
P4_K_AK2(ENB)
P4_K_AK2(ENB)
P3_K_AK1
nP3_WAIT_AK1
nn#P0_AK1
#P0_1_AK1
nn#P2_AK1
nn#P1_AK1
nn#P1_AK1
SD_CLK
circuit
SDCLK_ENB
SDCLK_ENB
O.C.
8
35:5
35:5
#P0_2_AK1
SEL_ADJ_Y/M/C/K
P3_K_AK2
nP3_WAIT_AK2
nSEL_ADJ_K
3
nP2_L_AK2
nP1_L_AK2
nP0_L_AK2
nP1_L_AK2
nP0_L_AK2
nSEL_SH
nn#P0_AK2
#P0_1_AK2
nn#P2_AK2
nn#P1_AK2
nn#P1_AK2
#P0_2_AK2
P3_C_AK1
P3_WAIT_AK1
P3_C_AK2
P3_WAIT_AK2
nSEL_ADJ_C
P3_ADJ
P3_ADJ
#P0_3_AK2
O.C.
Main scanning,
Sub scanning
timing control
MX-7500N BLOCK DIAGRAM / ブ ロ ッ ク図 1 – 9
7. SERIAL COMMUNICATION / シ リ アル通信
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Click on the first or last page to see other MX-6500N / MX-7500N (serv.man30) service manuals if exist.