MX-5500N, MX-6200N, MX-7000N (serv.man9). FULL CIRCUIT DIAGRAM 55 62 7000 LCX2 3 FNX3 4 PNX2A-D RBX2 CFX1 FXX1 — Sharp Copying Equipment Peripheral (repair manual). Page 26

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MX7000N  CIRCUIT DIAGRAM / 回路図  2 – 19
C204
0.1uF(B)
R202
33J
C405
0.1uF(B)
CP744
BR142
8.2KJx4
8
1
7
2
6
3
5
4
BR130
8.2KJx4
8
1
7
2
6
3
5
4
CP746
L10 BLM15AG121SN1(1005)
1
2
CP817
CP263
R201
33J
BR137
47Jx4
8
1
7
2
6
3
5
4
BR115
8.2KJx4
8
1
7
2
6
3
5
4
CP1118
R199
100J
R189
33J
CP262
R204
47J
R734
47J
R185
33J
R188
100J
CP739
R184
470J
CP265
CP264
R211
47J
CP750
R192
33J
BR119
8.2KJx4
8
1
7
2
6
3
5
4
R196
49.9F
L9
BLM15AG121SN1(1005)
1
2
C206
0.1uF(B)
R206
47J
R190
33J
R208
47J
CP747
C360
0.1uF(B)
CP745
CP1120
BR118
8.2KJx4
8
1
7
2
6
3
5
4
BR143
8.2KJx4
8
1
7
2
6
3
5
4
R193
47J
C205
0.1uF(B)
R209
47J
BR116
8.2KJx4
8
1
7
2
6
3
5
4
CP748
BR117
8.2KJx4
8
1
7
2
6
3
5
4
R200
33J
IC21D
Image_System_Chip_15
pci1_ad[31]
pci1_ad[30]
pci1_ad[29]
pci1_ad[28]
pci1_ad[27]
pci1_ad[26]
pci1_ad[25]
pci1_ad[24]
pci1_ad[23]
pci1_ad[22]
pci1_ad[21]
pci1_ad[20]
pci1_ad[19]
pci1_ad[18]
pci1_ad[17]
pci1_ad[16]
pci1_ad[15]
pci1_ad[14]
pci1_ad[13]
pci1_ad[12]
pci1_ad[11]
pci1_ad[10]
pci1_ad[9]
pci1_ad[8]
pci1_ad[7]
pci1_ad[6]
pci1_ad[5]
pci1_ad[4]
pci1_ad[3]
pci1_ad[2]
pci1_ad[1]
pci1_ad[0]
pci1_req5_l
AL27
pci1_req4_l
AN27
pci1_req3_l
AL28
pci1_req2_l
AP28
pci1_req1_l
AN28
pci1_gnt5_l
AK27
pci1_gnt4_l
AP27
pci1_gnt3_l
AP29
pci1_gnt2_l
AL29
pci1_gnt1_l
AN29
pci1_cbe[3]
pci1_cbe[2]
pci1_cbe[1]
pci1_cbe[0]
pci1_clki
AP17
pci1_par
AJ22
pci1_use_cpu
AJ27
pci1_idsel
AL25
pci1_lock_l
AP21
pci1_devsel_l
AP22
pci1_serr_l
AL22
pci1_stop_l
AN22
pci1_frame_l
AL23
pci1_perr_l
AM22
pci1_irdy_l
AK23
pci1_trdy_l
AJ23
pci1_into_l
AM29
pci1_inti_l
AK28
pllvdd_pci1
AL18
pllvss_pci1
AN17
bzrset_pci1
AP30
bzvdd_pci1
AN31
pci2_ad[31]
pci2_ad[30]
pci2_ad[29]
pci2_ad[28]
pci2_ad[27]
pci2_ad[26]
pci2_ad[25]
pci2_ad[24]
pci2_ad[23]
pci2_ad[22]
pci2_ad[21]
pci2_ad[20]
pci2_ad[19]
pci2_ad[18]
pci2_ad[17]
pci2_ad[16]
pci2_ad[15]
pci2_ad[14]
pci2_ad[13]
pci2_ad[12]
pci2_ad[11]
pci2_ad[10]
pci2_ad[9]
pci2_ad[8]
pci2_req5_l
K33
pci2_req4_l
K32
pci2_req3_l
H31
pci2_req2_l
J34
pci2_req1_l
L29
pci2_gnt5_l
J30
pci2_gnt4_l
J33
pci2_gnt3_l
J31
pci2_gnt2_l
J32
pci2_gnt1_l
H34
pci2_cbe[0]
pci2_cbe[1]
pci2_cbe[2]
pci2_cbe[3]
pci2_clki
Y34
pci2_use_cpu
H33
pci2_par
T30
pci2_idsel
K31
pci2_lock_l
R34
pci2_serr_l
T29
pci2_perr_l
R33
pci2_stop_l
R31
pci2_devsel_l
P34
pci2_trdy_l
R30
pci2_irdy_l
P33
pci2_frame_l
R29
pci2_into_l
K30
pci2_inti_l
K29
pllvss_pci2
W29
pllvdd_pci2
W30
bzvdd_pci2
G31
bzrset_pci2
G34
pci2_ad[7]
pci2_ad[6]
pci2_ad[5]
pci2_ad[4]
pci2_ad[3]
pci2_ad[2]
pci2_ad[1]
pci2_ad[0]
Image_System_Chip 4/8
PCI1 IF
PCI2 IF
CP1117
R197
10KJ
CP740
R733
47J
R186
33J
R203
33J
C207
0.1uF(B)
BR135
47Jx4
6
3
7
2
8
1
5
4
R194
47J
CP1119
C202
150pF
R187
10KJ
CP261
CP884
BR144
8.2KJx4
8
1
7
2
6
3
5
4
CP749
CP741
R205
47J
CP743
R198
33J
CP742
C203
150pF
R191
47J
CP849
BR141
8.2KJx4
8
1
7
2
6
3
5
4
CP260
R210
47J
R212
49.9F
CP1038
R183
470J
PLLVDD_PCI2
PCI2_AD24
PLLVDD_PCI1
PCI1_AD23
SA_PCI1_CLK
SA_PCI2_CLK
+3.3V
+3.3V
+3.3V
+1.2V
+1.2V
+3.3V
DGND
DGND
+3.3V_SA
+3.3V_SA
SA_PCI1_CLK
{4}
SA_PCI2_CLK
{4}
PCI2_INTA_PU
{7,16,33,36}
IDE_GNT
{16}
IDE_REQ
{16}
PCI2_IRDY
{16,36}
PCI2_TRDY
{16,36}
PCI2_DEVSEL
{16,36}
PCI2_FRAME
{16,36}
PCI2_STOP
{16,33,36}
PCI2_PERR
{16,33,36}
PCI2_SERR
{16,33,36}
PCI2_PAR
{16,36}
PCI1_FRAME
{23}
PCI1_TRDY
{23}
PCI1_IRDY
{23}
PCI1_SERR
{17,23,33}
PCI1_INTA_PU
{7,17,23,33}
PCI1_DEVSEL
{23}
PCI1_STOP
{17,23,33}
PCI1_PAR
{23}
PCI1_PERR
{17,23,33}
MAC_REQ
{17}
MAC_GNT
{17}
IF_REQ
{23}
IF_GNT
{23}
EXT_REQ
{33}
EXT_GNT
{33}
ICU_REQ
{36}
ICU_GNT
{36}
EXTBR_GNT
{33}
EXTBR_REQ
{33}
p-p in
bus s/t/s oi
bus s/t/s io
bus s/t/s oi
bus s/t/s io
bus s/t/s io
bus o/d io
bus s/t/s in
bus s/t/s io
bus o/d io
p-p in
p-p o/d out
p-p io
p-p in
p-p in
p-p in
p-p in
p-p io
p-p out
p-p out
p-p out
p-p out
5
5
4
4
3
3
D
C
B
A
MFPC PWB (SYSTEM ASIC PCI-1,2)
MX7000N  CIRCUIT DIAGRAM / 回路図  2 – 20
BR128
10KJx4
8
1
7
2
6
3
5
4
BR154
10KJx4
81
72
63
54
BR140
33Jx4
8
1
7
2
6
3
5
4
BR155
10KJx4
81
72
63
54
BR156
10KJx4
81
72
63
54
BR159
10KJx4
8
1
72
63
54
BR126
10KJx4
8
1
7
2
6
3
5
4
BR152
33Jx4
8
1
7
2
6
3
5
4
BR136
33Jx4
8
1
7
2
6
3
5
4
BR132
33Jx4
8
1
7
2
6
3
5
4
BR150
33Jx4
8
1
7
2
6
3
5
4
BR139
33Jx4
8
1
7
2
6
3
5
4
BR160
10KJx4
81
72
63
54
BR151
33Jx4
8
1
7
2
6
3
5
4
BR146
33Jx4
8
1
7
2
6
3
5
4
BR129
33Jx4
8
1
7
2
6
3
5
4
BR147
33Jx4
8
1
7
2
6
3
5
4
BR145
33Jx4
8
1
7
2
6
3
5
4
BR122
10KJx4
8
1
7
2
6
3
5
4
BR157
10KJx4
81
72
63
54
BR138
33Jx4
8
1
7
2
6
3
5
4
BR133
33Jx4
8
1
7
2
6
3
5
4
15
d[31]
AJ26
d[30]
AK26
d[29]
AL26
d[28]
AJ25
d[27]
AK25
d[26]
AL24
d[25]
AK24
d[24]
AJ24
d[23]
AM26
d[22]
AM25
d[21]
AN26
d[20]
AP26
d[19]
AN25
d[18]
AP25
d[17]
AN24
d[16]
AP24
d[15]
AP20
d[14]
AN19
d[13]
AP19
d[12]
AN18
d[11]
AJ21
d[10]
AM21
ad[9]
AL21
ad[8]
AL20
ad[7]
AL19
ad[6]
AM18
ad[5]
AK20
ad[4]
AK19
ad[3]
AK18
ad[2]
AJ20
ad[1]
AJ18
ad[0]
AJ19
be[3]
AN23
be[2]
AP23
be[1]
AN21
be[0]
AN20
d[31]
M29
d[30]
L30
d[29]
L31
d[28]
M31
d[27]
M30
d[26]
N32
d[25]
N29
d[24]
P32
d[23]
K34
d[22]
L33
d[21]
L34
d[20]
M33
d[19]
M34
d[18]
N33
d[17]
N34
d[16]
P29
d[15]
V34
d[14]
V33
d[13]
W34
d[12]
W33
d[11]
N31
d[10]
P31
ad[9]
T31
ad[8]
U31
be[0]
U34
be[1]
U33
be[2]
T34
be[3]
T33
ad[7]
U32
ad[6]
U30
ad[5]
U29
ad[4]
V30
ad[3]
V32
ad[2]
V31
ad[1]
W31
ad[0]
V29
4/8
BR124
10KJx4
8
1
7
2
6
3
5
4
BR162
10KJx4
8
1
72
63
54
BR121
10KJx4
8
1
7
2
6
3
5
4
BR127
10KJx4
8
1
7
2
6
3
5
4
BR120
10KJx4
8
1
7
2
6
3
5
4
BR131
33Jx4
8
1
7
2
6
3
5
4
BR161
10KJx4
81
72
63
54
BR123
10KJx4
8
1
7
2
6
3
5
4
BR125
10KJx4
8
1
7
2
6
3
5
4
BR149
33Jx4
8
1
7
2
6
3
5
4
BR148
33Jx4
8
1
7
2
6
3
5
4
BR158
10KJx4
81
72
63
5
4
BR134
33Jx4
8
1
7
2
6
3
5
4
BR153
33Jx4
8
1
7
2
6
3
5
4
PCI2_AD17
PCI2_AD16
PCI2_AD31
PCI2_AD0
PCI2_AD6
PCI2_AD11
PCI2_AD5
PCI2_AD21
PCI2_AD9
PCI2_AD23
PCI2_AD24
PCI2_AD28
PCI2_AD12
PCI2_AD15
PCI2_AD7
PCI2_AD19
PCI2_AD26
PCI2_AD27
PCI2_AD30
PCI2_AD14
PCI2_AD29
PCI2_AD20
PCI2_AD13
PCI2_AD2
ISCPCI1_AD28
ISCPCI1_AD29
ISCPCI1_AD30
ISCPCI1_AD31
ISCPCI1_AD24
ISCPCI1_AD25
ISCPCI1_AD26
ISCPCI1_AD27
ISCPCI1_AD4
ISCPCI1_AD5
ISCPCI1_AD6
ISCPCI1_AD7
ISCPCI1_AD16
ISCPCI1_AD17
ISCPCI1_AD18
ISCPCI1_AD19
ISCPCI1_AD20
ISCPCI1_AD21
ISCPCI1_AD22
ISCPCI1_AD23
ISCPCI1_AD8
ISCPCI1_AD9
ISCPCI1_AD10
ISCPCI1_AD11
ISCPCI1_AD12
ISCPCI1_AD13
ISCPCI1_AD14
ISCPCI1_AD15
ISCPCI1_AD0
ISCPCI1_AD1
ISCPCI1_AD2
ISCPCI1_AD3
PCI1_CBE2
PCI1_CBE0
PCI1_CBE1
PCI1_CBE3
PCI1_AD27
PCI1_AD0
PCI1_AD2
PCI1_AD19
PCI1_AD31
PCI1_AD11
PCI1_AD15
PCI1_AD1
PCI1_AD12
PCI1_AD22
PCI1_AD25
PCI1_AD21
PCI1_AD29
PCI1_AD24
PCI1_AD30
PCI1_AD10
PCI1_AD20
PCI1_AD5
PCI1_AD13
PCI1_AD18
PCI1_AD3
PCI1_AD17
PCI1_AD23
PCI1_AD7
PCI1_AD26
PCI1_AD4
PCI1_AD6
PCI1_AD8
PCI1_AD14
PCI1_AD16
PCI1_AD9
PCI1_AD28
PCI2_CBE3
PCI2_CBE2
PCI2_CBE0
PCI2_CBE1
PCI2_AD3
PCI2_AD25
PCI2_AD22
PCI2_AD1
PCI2_AD10
PCI2_AD18
PCI2_AD4
PCI2_AD8
+3.3V
+3.3V
PCI2_AD[31:0] {16,36}
PCI2_CBE[3:0] {16,36}
PCI1_AD[31:0] {23}
PCI1_CBE[3:0] {23}
3
3
2
2
1
1
D
C
B
A
10/42
MX7000N  CIRCUIT DIAGRAM / 回路図  2 – 21
CP463
CP303
CP331
CP337
CP319
C214
0.1uF(B)
CP305
C756
0.1uF(B)
IC21C
Image_System_Chip_15
lbus_dat[31]
AM6
lbus_dat[30]
AN6
lbus_dat[29]
AK8
lbus_dat[28]
AP6
lbus_dat[27]
AJ9
lbus_dat[26]
AL7
lbus_dat[25]
AN7
lbus_dat[24]
AP7
lbus_dat[23]
AK10
lbus_dat[22]
AN8
lbus_dat[21]
AJ10
lbus_dat[20]
AL9
lbus_dat[19]
AP8
lbus_dat[18]
AM9
lbus_dat[17]
AK9
lbus_dat[16]
AN9
lbus_dat[15]
AL8
lbus_dat[14]
AJ11
lbus_dat[13]
AP9
lbus_dat[12]
AK11
lbus_dat[11]
AM10
lbus_dat[10]
AN10
lbus_dat[9]
AK12
lbus_dat[8]
AJ12
lbus_dat[7]
AP10
lbus_dat[6]
AL11
lbus_dat[5]
AN11
lbus_dat[4]
AP11
lbus_dat[3]
AL10
lbus_dat[2]
AJ13
lbus_dat[1]
AN12
lbus_dat[0]
AL12
lbus_dma_req_l[3]
AK15
lbus_dma_req_l[2]
AM14
lbus_dma_req_l[1]
AP13
lbus_dma_req_l[0]
AL14
lbus_dma_ack_l[3]
AP14
lbus_dma_ack_l[2]
AL15
lbus_dma_ack_l[1]
AN14
lbus_dma_ack_l[0]
AJ15
lbus_dma_tc_l[3]
AL16
lbus_dma_tc_l[2]
AJ16
lbus_dma_tc_l[1]
AN15
lbus_dma_tc_l[0]
AK16
lbus_gen_cs_l[3]
AN5
lbus_gen_cs_l[2]
AN4
lbus_gen_cs_l[1]
AJ7
lbus_gen_cs_l[0]
AL5
lbus_ale
AP12
lbus_oe_l
AM13
lbus_we_l
AL13
lbus_wait_l(PU)
AJ14
lbus_buf_en_l
AN13
lbus_clko
AP4
lbus_boot_cs_l
AK6
uart_clki
AN16
uart_rxd[1]
AJ17
uart_rxd[0]
AK17
uart_txd[1]
AL17
uart_txd[0]
AP16
uart_txdrdy_l(IN,PU)
AM17
uart_rxdrdy_l
AP15
LSIPROCMON
D3
LSISCANENABLE
D2
LSI_IDDT
F5
LSI_TN
D1
LSI_POWERON_GO
G6
LSI_TRSTN(PU)
AN3
LSI_TMS(PU)
AK5
LSI_TDO
AP3
LSI_TCK
AJ6
LSI_TDI(PU)
AM2
eeprom_dat[1]
AK4
eeprom_dat[0]
AL1
smic_clki
AN30
pllvdd_smic
AM30
pllvss_smic
AL30
div_mode[1](PU)
AP31
div_mode[0](PU)
AK29
eeprom_clko[1]
AH6
eeprom_clko[0]
AM1
mst_por_l
AG31
pllvdd_mst
AE33
pllvss_mst
AD30
mst_clki
AE34
lbus_dma_cs_l[3]
AL6
lbus_dma_cs_l[2]
AJ8
lbus_dma_cs_l[1]
AP5
lbus_dma_cs_l[0]
AK7
Image_System_Chip 3/8
LOCAL BUS IF
UART
JTAG / SYSTEM
I2C
SMIC
CLOCK DEV.
Master Clock
PU
PU
CP300
CP380
CP476
CP325
CP393
C219
0.1uF(B)
C216
470pF
CP382
CP9
R231
1KJ
CP323
CP307
BR168
33Jx4
8
1
7
2
6
3
5
4
R736
22J
CP338
R
BR166
33Jx4
8
1
7
2
6
3
5
4
CP478
CP332
CP320
R228
1KJ
BR172
33Jx4
8
1
7
2
6
3
5
4
AS2
CAT24FC
C217
150pF
CP302
R217
47KJ
BR167
33Jx4
8
1
7
2
6
3
5
4
CP334
CP383
CP465
CP327
CP286
CP299
CP460
CP461
CP301
CP456
CP317
R737
22J
CP318
BR165
33Jx4
8
1
7
2
6
3
5
4
CP475
CP464
CP333
CP335
CP466
CP472
BR174
33Jx4
8
1
7
2
6
3
5
4
BR173
22Jx4
8
1
7
2
6
3
5
4
CP308
R224
2.2KJ
BR171
33Jx4
8
1
7
2
6
3
5
4
CP339
R233
4.7KJ
CP326
CP471
CP329
CP381
R236
10KJ
R235
33J
CP480
BR175
33Jx4
8
1
7
2
6
3
5
4
R213
10KJ
CP304
R232
2.2KJ
C215
150pF
CP324
BR170
33Jx4
8
1
7
2
6
3
5
4
CP336
R220
22J
CP328
CP387
CP457
R229
X_10KJ
CP424
CP459
R218
33J
C218
0.1uF(B)
CP321
BR176
33Jx4
8
1
7
2
6
3
5
4
CP330
C757
0.1uF(B)
C213
0.1uF(B)
CP458
CP322
CP477
L12
BLM15AG121SN1(1005)
12
CP429
CP266
R222
2.2KJ
L11
BLM15AG121SN1(1005)
12
BR169
33Jx4
8
1
7
2
6
3
5
4
R234
33J
CP474
CP462
CP306
DSW_DIV_MODE0
SA_SDA1
SMIC_CLK
DSW_DIV_MODE1
SA_UART_RXD1
SA_UART_TXD1
DSW_DIV_MODE1
DSW_DIV_MODE0
SA_SCL1
SA_SDA1
SA_SCL1
+3.3V
DGND
+1.2V
+1.2V
DGND
+3.3V
+3.3V
+3.3V
+3.3V
LBUS_DMA_ACK1
{20}
nSYSTEM_RST
{6}
LBUS_GEN_CS1
{18,25}
LBUS_GEN_CS2
{18,43}
LBUS_DMA_CS0
{21}
LBUS_DMA_TC0
{20}
SA_LBUS_OE
{18}
LBUS_GEN_CS3
{18,21}
ALE
{18}
SA_LBUS_WE
{18}
LBUS_DMA_TC1
{20}
SA_LBUS_WAIT
{18}
SA_MST_CLK
{4}
SA
LBUS_DMA_CS1
{21}
SA_SDA0
{10,35}
LBUS_DMA_REQ0
{20}
LBUS_DMA_CS2
{18,42}
LBUS_BOOT_CS
{25}
LBUS_DMA_REQ1
{20}
LBUS_DMA_ACK0
{20}
SMIC_CLK
{5}
LBUS_GEN_CS0
{18,25}
GPO_EEP_WP
{43}
SA_UART_TXD0_O
{32}
SA_UART_RXD0_I
{32}
nREADDIR
{18}
5
5
4
4
3
3
D
C
B
A
MFPC PWB (SYSTEM ASIC LOCAL, SYSTEM)
0.5A
MX7000N  CIRCUIT DIAGRAM / 回路図  2 – 22
C212
X_0.1uF(B)
C220
0.1uF(B)
C210
X_0.1uF(B)
R215
X_33J
R230
X_10KJ
S2
AT24FC256PI
CN4
X_S3B-PH-SM3-TB
1
2
3
R223
4.7KJ
IC27
X_MAX3232ECAE(16SSOP)
MAXIM
TIN1
11
ROUT1
12
ROUT2
9
TOUT1
14
TOUT2
7
RIN1
13
RIN2
8
C1+
1
C1-
3
C2+
4
C2-
5
V+
2
V-
6
GND
15
VCC
16
TIN2
10
C208
X_0.1uF(B)
C209
X_0.1uF(B)
7
R216
X_33J
R229
X_10KJ
C211
X_0.1uF(B)
IC28
8PIN DIP SOCKET
A0
1
A1
2
GND
4
SDA
5
SCL
6
WP
7
VCC
8
A2
3
AD1
AD9
AD22
AD26
AD17
AD2
AD10
AD23
AD27
AD18
AD3
AD11
AD28
AD19
AD4
AD12
AD29
AD5
AD21
AD13
AD30
AD6
AD14
AD31
AD7
AD24
AD15
AD0
AD20
AD8
AD25
AD16
CL1
SA_UART_TXD1
SA_UART_RXD1
+3.3V
+3.3V
3V
AD[31:0]
{18,21,25}
SA_UART_CLK {5}
SA_SCL0 {10,35}
TEST_JTRST1 {7,20,44}
TEST_JTMS1 {7,44}
TEST_JTCK1 {7,44}
SA_JTAG_TDO {44}
SA_JTAG_TDI {44}
3
3
2
2
1
1
D
C
B
A
11/42
MX7000N  CIRCUIT DIAGRAM / 回路図  2 – 23
BR178
10Jx4
8
1
7
2
6
3
5
4
Ima
video_dat_
AF29
video_dat_
AJ34
video_dat_
AJ31
video_dat_
AJ33
video_dat_
AJ32
video_dat_
AH30
video_dat_
AG29
video_dat_
AK34
video_dat_
AG33
video_dat_
AH31
video_dat_
AH33
video_dat_
AG30
video_dat_
AF32
video_dat_
AG34
video_dat_
AE30
video_dat_
AE29
scan_dat_y
AC30
scan_dat_y
AD33
scan_dat_y
AD31
scan_dat_y
AB29
scan_dat_m
AC33
scan_dat_m
AE31
scan_dat_m
AC34
scan_dat_m
AB32
scan_dat_c
AC31
scan_dat_c
AA29
scan_dat_c
AB33
scan_dat_c
AB31
scan_dat_k
AB34
scan_dat_k
AA31
scan_dat_k
AA32
scan_dat_k
Y30
video_vsyn
AJ29
video_vsyn
AN32
video_vsyn
AM33
video_vsyn
AK30
video_hsyn
AM34
video_hsyn
AJ30
video_hsyn
AL34
video_hsyn
AH29
video_hsyn
AF31
video_hsyn
AF33
video_hsyn
AF30
video_hsyn
AD29
N/C
M6
N/C
AC6
N/C
AJ3
N/C
AJ28
N/C
AC29
N/C
Y33
N/C
G33
N/C
C17
Image_
BR177
10Jx4
8
1
7
2
6
3
5
4
BR180
10Jx4
8
1
7
2
6
3
5
4
BR179
10Jx4
8
1
7
2
6
3
5
4
R239
22J
R240
47KJ
SCAN_DATB_I3
SCAN_DATB_I2
SCAN_DATB_I1
SCAN_DATB_I0
SCAN_DATG_I3
SCAN_DATG_I2
SCAN_DATG_I1
SCAN_DATG_I0
SCAN_DATR_I3
SCAN_DATR_I2
SCAN_DATR_I1
SCAN_DATR_I0
VIDEO_DAT_K3
VIDEO_DAT_K2
VIDEO_DAT_K1
VIDEO_DAT_K0
VIDEO_DAT_M3
VIDEO_DAT_M2
VIDEO_DAT_M1
VIDEO_DAT_M0
VIDEO_DAT_Y3
VIDEO_DAT_Y2
VIDEO_DAT_Y1
VIDEO_DAT_Y0
VIDEO_DAT_C3
VIDEO_DAT_C2
VIDEO_DAT_C1
VIDEO_DAT_C0
VIDEO_DAT_C4
VIDEO_DAT_C5
VIDEO_DAT_K4
VIDEO_DAT_K5
VIDEO_DAT_M4
VIDEO_DAT_M5
VIDEO_DAT_Y4
VIDEO_DAT_Y5
VIDEO_DAT_Y3
VIDEO_DAT_Y2
VIDEO_DAT_Y1
VIDEO_DAT_Y0
VIDEO_DAT_M3
VIDEO_DAT_M2
VIDEO_DAT_M1
VIDEO_DAT_M0
VIDEO_DAT_K3
VIDEO_DAT_K2
VIDEO_DAT_K1
VIDEO_DAT_K0
VIDEO_DAT_C3
VIDEO_DAT_C2
VIDEO_DAT_C1
VIDEO_DAT_C0
+3.3V
SA_VIDEO_HSYNC_I
{30,36}
SA_VIDEO_VSYNC_K_I
{30,36}
SA_VIDEO_VSYNC_C_I
{30,36}
SA_VIDEO_VSYNC_M_I
{30,36}
SA_VIDEO_VSYNC_Y_I
{30,36}
SA_VIDEO_HSYNC_O
{30,36}
VIDEO_DAT_K[5:0]
{30,36}
VIDEO_DAT_M[5:0]
{30,36}
VIDEO_DAT_Y[5:0]
{30,36}
VIDEO_DAT_C[5:0]
{30,36}
VIDEO_DAT_C[5:0] {30,36}
VIDEO_DAT_K[5:0] {30,36}
VIDEO_DAT_M[5:0] {30,36}
VIDEO_DAT_Y[5:0] {30,36}
VIDEO_DAT_C[5:0] {30,36}
VIDEO_DAT_K[5:0] {30,36}
VIDEO_DAT_M[5:0] {30,36}
VIDEO_DAT_Y[5:0] {30,36}
SCAN_DATB_I[3:0]
{36}
SCAN_DATG_I[3:0]
{36}
SCAN_DATR_I[3:0]
{36}
SA_VIDEO_VSYNC_Y_I {30,36}
SA_VIDEO_VSYNC_M_I {30,36}
SA_VIDEO_VSYNC_C_I {30,36}
SA_VIDEO_VSYNC_K_I {30,36}
SA_VIDEO_VSYNC_C_I
{30,36}
SA_VIDEO_VSYNC_M_I
{30,36}
SA_VIDEO_VSYNC_Y_I
{30,36}
SA_VIDEO_VSYNC_K_I
{30,36}
SA_VIDEO_HSYNC_I {30,36}
SA_VIDEO_HSYNC_I
{30,36}
SA_VIDEO_HSYNC_O {30,36}
SA_VIDEO_HSYNC_O
{30,36}
5
5
4
4
3
3
D
C
B
A
MFPC PWB (SYSTEM ASIC VIDEO OUT/SCAN IN)

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