Sharp AR-P16 (serv.man2) Service Manual ▷ View online
AR-P16 PRINT CONTROL PWB / プリントコントロール PWB 2 - 3
5
5
6
6
7
7
8
8
A
B
C
D
R508
10K
NO ASM
R524
10K
NO ASM
R531
10K
NO ASM
R519
10K
R518
10K
NO ASM
R516
10K
R525
10K
NO ASM
R503
10K
R526
10K
R509
10K
R561
10K
R523
10K
R528
10K
NO ASM
R447
10K
NO ASM
R512
10K
R511
1K
NO ASM
R534
10K
R560
10K
NO ASM
R533
10K
NO ASM
R454
10K
R530
10K
R506
10K
R515
10K
NO ASM
R502
1K
NO ASM
R505
10K
NO ASM
R527
10K
R514
10K
BA[0..1]
MA2
MA5
MA[0..13]
MA9
MA7
MA6
MA8
MA3
MA1
MA4
MA10
BA0
MDL0
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
VCC-107IO
FOEN
7,9
BA[0..1]
7,11
RCS0N
7,9
MA[0..13]
7,11
MDL[0..31]
10,11,12
Boot Memory Location [/RCS0]
0 : Indicates that boot ROM is located on the PCI bus
1 : Indicates that boot ROM is located on local processor/memory data bus
0 MPC107 is a PCI agent device
1 MPC107 is a PCI master (host) device
0 : PCI arbiter enabled
1 : PCI arbiter disabled
[SDMA8, SDMA7]
11 : 8-ohm drive capability
10 : 13.3-ohm drive capability
01 : 20-ohm drive capability
00 : 40-ohm drive capability
0 : High drive capability on PCI signals (25 ohm)
1 : Medium drive capability on PCI signals (50 ohm)
0 : High drive capability on CPU signals (20 ohm)
1 : Medium drive capability on CPU signals (40 ohm)
0 : DLL lock range extended
1 : Standard DLL range
ROM Data Width [MDL(0), FOE]
0 : The MPC107 is configured for address map A
(not supported when operating in PCI agent mode)
1 : The MPC107 is configured for address map B
[SDMA4, SDMA3, '0'] (UM-Section 4.3.2)
000 : Recommended for 66MHz PCI bus
100 : Recommended for 33MHz PCI bus
For ROM/FLASH chip select #0/1
RCS0 RCS1 MDL0 FOE MCCR4-bit17
(bit) (bit)
------------------------------------------------
64 64 1 0 0
64 8 1 0 1
8 64 1 1 0
8 8 1 1 1
[MPC107 RESET CONFIGURATION] (UM-Section 2.4)
Initial Address Map [SDBA0]
MPC107 Host Mode [SDMA10]
PCI Arbiter [SDMA9]
1 : 20-ohm data bus drive capability; when this is selected,
only 8-ohm or 13.3-ohm drive capability is allowed for SDMA7
0 : 40-ohm data bus drive capability; when this is selected,
only 20-ohm or 40-ohm drive capability is allowed for SDMA7
Driver capability for MDH[0:31], MDL[0:31], PAR[0:7], and RCS1 [SDMA8]
Driver capability for address signals (RAS/CS[0:7], CAS/DQM[0:7], WE, FOE, RCS0,
RCS2, RCS3, SDBA0, SDRAS, SDCAS, CKE, AS, SDMA[13:0]) [SDMA7]
Driver capability for PCI and EPIC controller output signals [SDMA6]
Driver capability for SDA, SCL, CKO, QACK, and MCP as well as 60x output signals [SDMA5]
PCI output hold delay value (in nanoseconds) relative to PCI_SYNC_IN [SDMA4, SDMA3]
(Section 2.3.3)
0 : Clock flip enabled
1 : No clock flip
Clock flip disable [SDMA2]
DLL lock range extend [SDMA1]
-->
2/24
AR-P16 PRINT CONTROL PWB / プリントコントロール PWB 2 - 4
1
1
2
2
3
3
4
4
A
B
C
D
C54
0.1uF
JP5
GND
NO ASM
2
1
IC12
PJ1085CZ
IN
3
OUT
2
ADI
1
D4
RB451F
2
1
3
IC8C
74LCX14MTC
5
6
R122
0
C45
220uF/10V
+
IC8A
74LCX14MTC
1
2
JP8
GND
NO ASM
2
1
R2
200
R123
0
NO ASM
C38
10uF/16V
+
D5
RB051L-40
2
1
R121
0
NO ASM
ICT542
C56
0.1uF
C33
0.1uF
D1
LTL-1LHEE-002A
NO ASM
R177
120(F)
R124
0
C40
0.1uF
D3
RB451F
2
1
3
R174
200
C39
47uF/16V
+
ICT1101
C41
0.1uF
ICT1086
IC11
RC1117D33X
GND
1
IN
3
OUT
2
JP4
GND
NO ASM
2
1
C44
220uF/10V
+
JP9
GND
NO ASM
2
1
VCCP5V
VCC-CPUIO
VCCP5V
VCC
VCC-CPUIO
IVDD
IVDD
VCCP5V
VCC
VCCP5V = +5V_PRT from Engine I/F
VCC-CPUIO = 3.3V for CPU I/O (max. 1A)
IVDD = 2.0V for CPU core (max. 3A)
PRINT CONTROL PWB (POWER)
VCC = +3.3V from Engine I/F
[for IC8]
AR-P16 PRINT CONTROL PWB / プリントコントロール PWB 2 - 5
5
5
6
6
7
7
8
8
A
B
C
D
ICT835
R562
1K
C264
0.1uF
R613
0
NO ASM
R565
0
NO ASM
C277
220uF/10V
+
R2
200
IC50
RC1117D33X
GND
1
IN
3
OUT
2
ICT599
C271
10uF/16V
+
Q12
DTA114EKA
NO ASM
1
2
3
R556
0
D8
RB451F
2
1
3
R594
1K
NO ASM
ICT791
D9
RB451F
2
1
3
ICT773
ICT600
CN14
B3B-PH-K-K
1
1
2
2
3
3
R611
0
R615
0
R614
1K
R553
0
NO ASM
C33
0.1uF
002A
R636
0
NO ASM
C272
10uF/16V
+
R554
0
NO ASM
R593
0
NO ASM
C266
0.1uF
R612
0
R557
0
Q11
DTC114YKA
NO ASM
1
2
3
ICT20
R606
0
NO ASM
C265
0.1uF
01
R558
0
IC49
RC1117D25X
GND
1
IN
3
OUT
2
C263
0.1uF
R607
0
C276
220uF/10V
+
ICT327
Q13
DTC114YKA
1
2
3
R566
0
R555
0
VCCP5V
VCC-107IO
VCCP5V
VCC
VCC
VCCP5V
P24V_PRT
VCC
VCC
VCCP5V
VCCP5V
107-VCORE
PWM
15,16
FAN_PWM
16
FAN_PWM
16
ngine I/F
VCC-107IO = 3.3V for 107 I/O (max. 1A)
107-VCORE = 2.5V for 107 core (max. 1A)
[for IC8]
[FAN POWER CN]
3/24
AR-P16 PRINT CONTROL PWB / プリントコントロール PWB 2 - 6
ICT609
R328
0
NO ASM
NO ASM
ICT606
BR
E7
BG
H1
ABB
L7
DBG
K1
DBB
K5
TS
K7
AACK
N3
TT4
F11
TT3
C12
TT2
B12
TT1
D11
TT0
C10
TSIZ2
C9
TSIZ1
B9
TSIZ0
A9
TBST
A11
CI
C2
WT
C3
GBL
B1
TA
F1
TEA
J1
ARTRY
L6
NC
B3
NC
B4
NC
K9
NC
B5
NC
K11
INT
C11
SMI
A12
CKSTP_IN
B8
CKSTP_OUT
D7
MCP
B11
SRESET
E10
HRESET
B6
PLL_CFG0
A4
PLL_CFG1
A5
PLL_CFG2
A6
PLL_CFG3
A7
SYSCLK
H9
CL
K
O
UT
E3
TRST
A10
TCK
B10
TM
S
C8
TDI
B7
TDO
D9
AP3
C7
AP2
C6
TBEN
A2
BVSEL(
NC)
W1
L2VSEL(
NC)
A19
TLBI
SYNC
A3
DBW
O
D1
DR
TR
Y
H6
DBDI
S
G1
QA
CK
B2
QREQ
J3
RSR
V
D3
R
312
10K
IC
T698
0
BR73
10K
1
2
3
4
2
3
4
5
6
7
8
IC
T699
IC
T700
R308
10
IC
T701
BR64
10K
1
2
3
4
2
3
4
5
6
7
8
ICT613
R250
0
IC
T702
ICT1107
ICT614
R179
10
ICT1109
BR68
10K
1
2
3
4
2
3
4
5
6
7
8
ICT615
R325
0
ICT1154
ICT617
R4
200
ICT1110
R188
10
ICT619
R337
10
ICT1155
ICT621
BR61
10K
1
2
3
4
2
3
4
5
6
7
8
R326
0
NO ASM
NO ASM
ICT623
R251
0
NO ASM
ICT627
R178
10
R180
10
ICT616
BR62
10K
1
2
3
4
2
3
4
5
6
7
8
ICT618
BR66
10K
1
2
3
4
2
3
4
5
6
7
8
R324
10
ICT620
ICT1123
ICT622
R323
10
R336
10
NO ASM
ICT624
BR65
10K
1
2
3
4
5
6
7
8
ICT847
BR69
10K
1
2
3
4
2
3
4
5
6
7
8
R320
10
R333
0
R317
10
0
R318
10
D2
LTL-1LHEE-002A
NO ASM
NO ASM
R319
10
BR71
10K
1
2
3
4
5
6
7
8
6
7
8
R299
10
R
309
10K
NO ASM
ICT576
BR54
10K
1
2
3
4
2
3
4
5
6
7
8
0
R
310
10K
ICT114
ICT111
R332
0
NO ASM
0
ICT115
ICT112
IC
T706
R334
0
NO ASM
ICT116
IC
T707
R316
0
ICT117
R
311
10K
BR49
10K
1
2
3
4
2
3
4
5
6
7
8
BR51
10K
1
2
3
4
2
3
4
5
6
7
8
ICT34
ICT35
ICT35
IC
T705
R189
10
IC
T665
BR70
10K
1
2
3
4
2
3
4
5
6
7
8
ICT36
ICT37
ICT37
R187
10
IC
T708
R322
10
IC
T872
R
321
0
IC
T871
R330
0
NO ASM
BR21
10K
1
2
3
4
2
3
4
5
6
7
8
BR57
10K
1
2
3
4
2
3
4
5
6
7
8
R314
0
R327
0
NO ASM
NO ASM
R23
0
R
201
0
TT[0..4]
CPUPLL2
CPUPLL1
TT1
CA29
CA11
CA21
AP0
TT3
TT[0..4]
CA22
TT3
CA27
TT0
TT1
CA8
CA2
CA30
CPUPLL[0..3]
AP2
CA12
CA20
CPUPLL3
CA4
CA25
AP2
CPUPLL3
CA16
CA6
CPUPLL1
CA19
CA18
CA31
CA9
AP3
CPUPLL2
TT0
CA28
CA14
CA3
AP1
TT4
CPUPLL0
TT2
AP[0..3]
CA17
CA13
TT2
CA26
CA24
AP3
CA1
TT4
CA5
CA7
CA7
CA23
CA10
CA15
CPUPLL0
CA0
TSIZ[0..2]
TSIZ0
TSIZ1
TSIZ2
VCC-CPUIO
VCC-CPUIO
VCC-CPUIO
CPUCLK
7
LV_HRSTN
9,16,19,21,23
MCPN
7,14
CKSTPIN
19
CKSTPON
19
SMIN
14,23
CPUINTN
7,14
ARTRYN
6,14,16,23
TAN
6,14,16,23
TEAN
6,14
GBLN
6,14,23
CIN
6,14
TSIZ[0..2]
6,14,23
TSN
6,14,16,23
AACKN
6,14,16,23
BG0N
6,14
DBG0N
6,14,23
BR0N
6,14,16
QREQN
6,19,23
LV_QACKN
19
SRSTN_CPU
19
LV_TRSTN
19
CPU_TCLK
19
CPU_TMS
19
CA[0..31]
5,6,14,23
GBLN
6,14,23
SMIN
14,23
BR0N
6,14,16
TBSTN
6,14,23
TAN
6,14,16,23
AACKN
6,14,16,23
TT[0..4]
6,14,23
TEAN
6,14
TSN
6,14,16,23
MCPN
7,14
TBSTN
6,14,23
ARTRYN
6,14,16,23
CKSTPIN
19
AP[0..3]
JTMS
7
JTCK
7
JTRST
7
TT[0..4]
6,14,23
CIN
6,14
DBG0N
6,14,23
WTN
6,14
DBBN
14
DBBN
14
ABBN
14
ABBN
14
CPUCLK_A
7
BR0N_CPU
16
(DBB_LED)
CPU PLL SETTINGS
CP0
CP1
CP2
CP3
BUS MULT
BUS CLK
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
OFF
OFF
3.5X
2X
7.5X
4.5X
3X
5.5X
4X
5X
6X
100
50-80
50-66
33-66
33-50
50-66
33-66
33-50
BY PASS
66-100
50-100
6.5X
<-- 66 x 4.5=300
H
H
H
H
H
H
H
H
H
66-100
50-80
33-50
33-50
33-50
8X
7X
10X
33
33-50
H
66 x 5.0=333
PRINT CONTROL PWB (XPC755-1)
66 x 5.5=366
66 x 5.5=400
66 x 5.5=400
1
1
2
2
3
3
4
4
A
B
C
D
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