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AL-840 (serv.man10)
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Service Manual
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Copying Equipment / AL800 840 Service Manual-Signal List
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Sharp AL-840 (serv.man10) Service Manual ▷ View online

[11] SIGNAL LIST
Signal
name
Device
Pin
No.
Input/
Output
Content
Remark
3.3V
ASIC
5
Power
3.3V
ASIC
20
Power
3.3V
ASIC
31
Power
3.3V
ASIC
44
Power
3.3V
ASIC
57
Power
3.3V
ASIC
69
Power
3.3V
ASIC
88
Power
3.3V
ASIC
95
Power
3.3V
ASIC
249
Power
5V
ASIC
18
Power
5V
ASIC
90
Power
5V
ASIC
108
Power
5V
ASIC
121
Power
5V
ASIC
133
Power
5V
ASIC
146
Power
5V
ASIC
172
Power
5V
ASIC
185
Power
5V
ASIC
236
Power
A0
CPU
6
OUT
Address bus (NC-pull up)
A1
CPU
7
OUT
Address bus 
A10
CPU
17
OUT
Address bus
A11
CPU
18
OUT
Address bus
A12
CPU
20
OUT
Address bus
A13
CPU
21
OUT
Address bus
A14
CPU
22
OUT
Address bus
A15
CPU
23
OUT
Address bus
A16
CPU
24
OUT
Address bus
A17
CPU
25
OUT
Address bus (NC)
A18
CPU
26
OUT
Address bus (NC-pull up)
A19
CPU
27
OUT
Address bus (NC-pull up)
A2
CPU
8
OUT
Address bus 
A20
CPU
29
OUT
Address bus (NC-pull up)
NC
A3
CPU
9
OUT
Address bus
A4
CPU
11
OUT
Address bus
A5
CPU
12
OUT
Address bus
A6
CPU
13
OUT
Address bus
A7
CPU
14
OUT
Address bus
A8
CPU
15
OUT
Address bus
A9
CPU
16
OUT
Address bus
ACK
ASIC
117
OUT
(NC)
APCSTT
ASIC
215
OUT
APC circuit (LSU) path
signal
AS-
CPU
90
OUT
AUTOFD
ASIC
115
IN
(NC)
BCLK
ASIC
177
OUT
CCD black level output latch
signal
BUSY
ASIC
118
OUT
(NC)
Busy1
ASIC
(ICU)
101
OUT
Busy signal. In the
compatible mode, driven to
HIGH when the engine
cannot receive data. In the
ECP mode, used to control
data transfer.
Busy2
ASIC
(ICU)
77
OUT
Busy signal. In the
compatible mode, driven to
HIGH when the engine
cannot receive data. In the
ECP mode, used to control
data transfer.
CAS_
ASIC
(ICU)
24
OUT
Column address select (ICU
DRAM area control)
CAS0
ASIC
61
OUT
CAS signal (image area
display signal) of DRUM
(page memory)
Signal
name
Device
Pin
No.
Input/
Output
Content
Remark
CAS1
ASIC
62
OUT
CAS signal (image area
display signal) of DRUM
(page memory)
CL_CNT
ASIC
220
OUT
Copy lamp control
(ON/OFF) signal
CL_IN
CPU
107
IN
Copy lamp light quantity
detection
NC
CLK
ASIC
(ICU)
132
OUT
Crystal oscillator connection
pin (Input side)
CLK2
ASIC
(ICU)
134
IN
Crystal oscillator connection
pin (Output side)
COE0
ASIC
141
OUT
Read enable signal to
SRAM before area
separation
CP
ASIC
176
OUT
A/D conversion IC latch
enable
CPUAD1
ASIC
13
IN
CPU address bus
CPUAD2
ASIC
12
IN
CPU address bus
CPUAD3
ASIC
11
IN
CPU address bus
CPUAD4
ASIC
10
IN
CPU address bus
CPUAD5
ASIC
9
IN
CPU address bus
CPUAD6
ASIC
7
IN
CPU address bus
CPUAD7
ASIC
6
IN
CPU address bus
CPUCLK
ASIC
253
IN
CPU system clock
CPUCLK
CPU
88
OUT
G/A system clock
CPUCS
ASIC
16
IN
CPU chip select signal
CPUD0
ASIC
248
IN/OUT CPU data bus
CPUD1
ASIC
247
IN/OUT CPU data bus
CPUD10
ASIC
237
IN/OUT CPU data bus
CPUD11
ASIC
235
IN/OUT CPU data bus
CPUD12
ASIC
234
IN/OUT CPU data bus
CPUD13
ASIC
233
IN/OUT CPU data bus
CPUD14
ASIC
232
IN/OUT CPU data bus
CPUD15
ASIC
231
IN/OUT CPU data bus
CPUD2
ASIC
246
IN/OUT CPU data bus
CPUD3
ASIC
245
IN/OUT CPU data bus
CPUD4
ASIC
244
IN/OUT CPU data bus
CPUD5
ASIC
243
IN/OUT CPU data bus
CPUD6
ASIC
242
IN/OUT CPU data bus
CPUD7
ASIC
241
IN/OUT CPU data bus
CPUD8
ASIC
240
IN/OUT CPU data bus
CPUD9
ASIC
238
IN/OUT CPU data bus
CPURD
ASIC
251
IN
CPU read signal
CPUSYNC
ASIC
14
OUT
Laser horizontal sync signal
to CPU
CPUSYNC
CPU
34
IN
Laser horizontal sync signal
CPUWR
ASIC
250
IN
CPU write signal
CS0
CPU
1
OUT
SRAM chip select bsignal
CS0
CPU
2
OUT
ERPOM chip select
CS2
CPU
128
OUT
ASIC chip select signal
CS4-
CPU
66
OUT
Expansion IC select signal
NC
D0
CPU
40
IN/OUT Data bus
D1
CPU
41
IN/OUT Data bus
D10
CPU
51
IN/OUT Data bus
D11
CPU
52
IN/OUT Data bus
D12
CPU
54
IN/OUT Data bus
D13
CPU
55
IN/OUT Data bus
D14
CPU
56
IN/OUT Data bus
D15
CPU
57
IN/OUT Data bus
D2
CPU
42
IN/OUT Data bus
D3
CPU
43
IN/OUT Data bus
D4
CPU
45
IN/OUT Data bus
D5
CPU
46
IN/OUT Data bus
D6
CPU
47
IN/OUT Data bus
D7
CPU
48
IN/OUT Data bus
11 – 1
Signal
name
Device
Pin
No.
Input/
Output
Content
Remark
D8
CPU
49
IN/OUT Data bus
D9
CPU
50
IN/OUT Data bus
DAH
CPU
111
IN
CCD reference voltage
(High)
DAL
CPU
112
IN
CCD reference voltage
(LOW)
Data11
ASIC
(ICU)
116
IN/OUT Data bus.
Data12
ASIC
(ICU)
115
IN/OUT Data bus.
Data13
ASIC
(ICU)
114
IN/OUT Data bus.
Data14
ASIC
(ICU)
111
IN/OUT Data bus.
Data15
ASIC
(ICU)
110
IN/OUT Data bus.
Data16
ASIC
(ICU)
107
IN/OUT Data bus.
Data17
ASIC
(ICU)
106
IN/OUT Data bus.
Data18
ASIC
(ICU)
105
IN/OUT Data bus.
Data21
ASIC
(ICU)
92
IN/OUT Data bus.
Data22
ASIC
(ICU)
89
IN/OUT Data bus.
Data23
ASIC
(ICU)
88
IN/OUT Data bus.
Data24
ASIC
(ICU)
86
IN/OUT Data bus.
Data25
ASIC
(ICU)
85
IN/OUT Data bus.
Data26
ASIC
(ICU)
84
IN/OUT Data bus.
Data27
ASIC
(ICU)
81
IN/OUT Data bus.
Data28
ASIC
(ICU)
80
IN/OUT Data bus.
Data31
ASIC
(ICU)
66
IN/OUT Data bus.
Data32
ASIC
(ICU)
65
IN/OUT Data bus.
Data33
ASIC
(ICU)
64
IN/OUT Data bus.
Data34
ASIC
(ICU)
62
IN/OUT Data bus.
Data35
ASIC
(ICU)
61
IN/OUT Data bus.
Data36
ASIC
(ICU)
60
IN/OUT Data bus.
Data37
ASIC
(ICU)
57
IN/OUT Data bus.
Data38
ASIC
(ICU)
56
IN/OUT Data bus.
DCRDY-
ASIC
203
OUT
Serial communication
request
DCRDY_
ASIC
(ICU)
6
IN
Command ready. Sends a
command to the PCU at
LOW.
DDATA
ASIC
(ICU)
17
OUT
Video data
DOP-
CPU
108
IN
Door open sensor
DPAGE-
CPU
110
IN
Print request signal from ICU
DPAGE_
ASIC
(ICU)
11
OUT
Page. Driven to LOW when
requesting the engine for
printing.
DPRIM-
CPU
33
IN
Communication port
initialize signal from ICU
DPRIM_
ASIC
(ICU)
14
OUT
DREADY-
ASIC
204
OUT
Engine ready
Signal
name
Device
Pin
No.
Input/
Output
Content
Remark
DREADY_
ASIC
(ICU)
5
IN
Engine ready. Shows the
print enable state at LOW.
Turns HIGH during printing
or in case of an print error.
DSRDY-
CPU
101
IN
Serial communication
request from controller
DSRDY_
ASIC
(ICU)
8
OUT
Status ready. At LOW, the
PCU can send a status
signal.
EEPCK
CPU
95
OUT
Serial clock output
EEPD
CPU
96
OUT
Serial data I/O
ERROR
ASIC
205
OUT
Engine error to ICU
ERROR
ASIC
(ICU)
7
IN
Error. Turns HIGH in case
of an engine error.
ESACK
ASIC
100
IN
(NC)
ESCS
ASIC
101
IN
(NC)
ESPRD
ASIC
97
IN
(NC)
ESREQ
ASIC
99
OUT
(NC)
EXTAL
CPU
86
Clock
F_RXD
CPU
62
IN
FAX&PRINTER recpetion
buffer
NC
F_TXD
CPU
60
OUT
FAX&PRINTER send enable NC
f1
ASIC
169
OUT
CCD drive signal transfer
clock (First phase)
f2
ASIC
170
OUT
CCD drive signal transfer
clock (Second phase)
FAULT
ASIC
120
OUT
(NC)
FAXACK
ASIC
94
IN
(NC)
FAXCS
ASIC
96
IN
(NC)
FAXPRD
ASIC
92
IN
(NC)
FAXREQ
ASIC
93
OUT
(NC)
FIRQ-
CPU
31
IN
FAXPRINTER
NC
FORATFD
ASIC
(ICU)
130
IN
Fixed. (HIGH)
FORID1
ASIC
(ICU)
123
IN
ID ROM select (machine ID
No.)
FORID2
ASIC
(ICU)
124
IN
ID ROM select (machine ID
No.)
FORTEST
ASIC
(ICU)
121
IN
FORTEST
ASIC
(ICU)
122
IN
GND
ASIC
8
Power
GND
ASIC
19
Power
GND
ASIC
21
Power
GND
ASIC
34
Power
GND
ASIC
47
Power
GND
ASIC
60
Power
GND
ASIC
72
Power
GND
ASIC
89
Power
GND
ASIC
91
Power
GND
ASIC
98
Power
GND
ASIC
111
Power
GND
ASIC
124
Power
GND
ASIC
136
Power
GND
ASIC
149
Power
GND
ASIC
162
Power
GND
ASIC
175
Power
GND
ASIC
188
Power
GND
ASIC
239
Power
GND
ASIC
252
Power
GND
ASIC
254
Power
GND
ASIC
(ICU)
10
GND
GND
ASIC
(ICU)
18
GND
GND
ASIC
(ICU)
27
GND
11 – 2
Signal
name
Device
Pin
No.
Input/
Output
Content
Remark
GND
ASIC
(ICU)
36
GND
GND
ASIC
(ICU)
44
GND
GND
ASIC
(ICU)
50
GND
GND
ASIC
(ICU)
54
GND
GND
ASIC
(ICU)
59
GND
GND
ASIC
(ICU)
63
GND
GND
ASIC
(ICU)
67
GND
GND
ASIC
(ICU)
72
GND
GND
ASIC
(ICU)
78
GND
GND
ASIC
(ICU)
83
GND
GND
ASIC
(ICU)
87
GND
GND
ASIC
(ICU)
91
GND
GND
ASIC
(ICU)
96
GND
GND
ASIC
(ICU)
102
GND
GND
ASIC
(ICU)
108
GND
GND
ASIC
(ICU)
112
GND
GND
ASIC
(ICU)
117
GND
GND
ASIC
(ICU)
127
GND
GND
ASIC
(ICU)
131
GND
GND
ASIC
(ICU)
135
IN
GND
GND
ASIC
(ICU)
138
GND
GND
ASIC
(ICU)
144
GND
HLON
CPU
72
OUT
Heater lamp control 
HSYNC
ASIC
83
OUT
(NC)
HWR
CPU
92
OUT
Write signal (High address)
I/O
ASIC
(ICU)
119
OUT
IDIN0
ASIC
178
IN
Image scan data (after 8 bit
A/D conversion)
IDIN1
ASIC
179
IN
Image scan data (after 8 bit
A/D conversion)
IDIN2
ASIC
180
IN
Image readign data (10 bit
A/D conversion)
IDIN3
ASIC
181
IN
Image scan data (after 11
bit A/D conversion)
IDIN4
ASIC
182
IN
Image scan data (after 12
bit A/D conversion)
IDIN5
ASIC
183
IN
Image scan data (after 13
bit A/D conversion)
IDIN6
ASIC
184
IN
Image scan data (after 14
bit A/D conversion)
IDIN7
ASIC
186
IN
Image reading data (16 bit
A/D conversion)
IETON_
ASIC
(ICU)
137
IN
IET circuit operation switch
INIT
ASIC
113
IN
(NC)
INTR
ASIC
15
OUT
Interrupt request signal
NC
INTROM
ASIC
(ICU)
142
IN
Signal
name
Device
Pin
No.
Input/
Output
Content
Remark
LD
ASIC
192
OUT
Laser drive signal
LDATAEN
ASIC
198
OUT
Laser enable (ON/OFF)
signal
LEND
ASIC
193
OUT
Laser APC signal
LEND-
ASIC
216
OUT
Line end signal
LEND_
ASIC
(ICU)
15
IN
Line end. When HIGH is
inputted, VDD is driven to
HIGH.
LWR
CPU
93
OUT
Write signal (Low address)
MAD0
ASIC
46
OUT
DRAM (page memory)
address bus
MAD1
ASIC
48
OUT
DRAM (page memory)
address bus
MAD10
ASIC
58
OUT
DRAM (page memory)
address bus
MAD11
ASIC
59
OUT
DRAM (page memory)
address bus
MAD2
ASIC
49
OUT
DRAM (page memory)
address bus
MAD3
ASIC
50
OUT
DRAM (page memory)
address bus
MAD4
ASIC
51
OUT
DRAM (page memory)
address bus
MAD5
ASIC
52
OUT
DRAM (page memory)
address bus
MAD6
ASIC
53
OUT
DRAM (page memory)
address bus
MAD7
ASIC
54
OUT
DRAM (page memory)
address bus
MAD8
ASIC
55
OUT
DRAM (page memory)
address bus
MAD9
ASIC
56
OUT
DRAM (page memory)
address bus
MASK_PEL
ASIC
(ICU)
125
IN
Parity_error of the status
register bit 11 is masked.
MCON
ASIC
218
OUT
Main charger ON
MDATA0
ASIC
39
IN/OUT DRAM (page memory) data
bus
MDATA1
ASIC
38
IN/OUT DRAM (page memory) data
bus
MDATA10
ASIC
27
IN/OUT DRAM (page memory) data
bus
MDATA11
ASIC
26
IN/OUT DRAM (page memory) data
bus
MDATA12
ASIC
25
IN/OUT DRAM (page memory) data
bus
MDATA13
ASIC
24
IN/OUT DRAM (page memory) data
bus
MDATA14
ASIC
23
IN/OUT DRAM (page memory) data
bus
MDATA15
ASIC
22
IN/OUT DRAM (page memory) data
bus
MDATA2
ASIC
37
IN/OUT DRAM (page memory) data
bus
MDATA3
ASIC
36
IN/OUT DRAM (page memory) data
bus
MDATA4
ASIC
35
IN/OUT DRAM (page memory) data
bus
MDATA5
ASIC
33
IN/OUT DRAM (page memory) data
bus
MDATA6
ASIC
32
IN/OUT DRAM (page memory) data
bus
MDATA7
ASIC
30
IN/OUT DRAM (page memory) data
bus
MDATA8
ASIC
29
IN/OUT DRAM (page memory) data
bus
MDATA9
ASIC
28
IN/OUT DRAM (page memory) data
bus
MEM0
ASIC
(ICU)
128
IN
Used to set the DRAM size.
11 – 3
Signal
name
Device
Pin
No.
Input/
Output
Content
Remark
MEM1
ASIC
(ICU)
129
IN
Used to set the DRAM size.
MEN-
ASIC
227
OUT
Main motor drive signal
MHPS
CPU
38
IN
Mirror home position sensor
MMT0
CPU
118
OUT
Main motor drive signal 1
MMT1
CPU
117
OUT
Main motor drive signal 2
MODE
ASIC
(ICU)
120
IN
At HIGH, IET-processed
video data is outputted. At
LOW, video data is
outputted by bypassing the
IET circuit.
MODE
CPU
106
AIN
Power monitoring
NC
MRMT0
CPU
122
OUT
Mirror motor control signal 1
MRMT1
CPU
121
OUT
Mirror motor control signal 2
MRMT2
CPU
120
OUT
Mirror motor control signal 3
MRMT3
CPU
119
OUT
Mirror motor control signal 4
MRPS1
CPU
116
OUT
Mirror motor power save 1
MRPS2
CPU
115
OUT
Mirror motor power save 2
nAck1
ASIC
(ICU)
104
OUT
Acknowledge
signal/Handshake signal in
the reverse mode
nAck2
ASIC
(ICU)
79
OUT
Acknowledge
signal/Handshake signal in
the reverse mode
nAck3
ASIC
(ICU)
55
OUT
Acknowledge
signal/Handshake signal in
the reverse mode
nAutoFd1
ASIC
(ICU)
98
IN
Auto feed signal/Handshake
signal in the reverse
mode/Command data
identification signal
nAutoFd2
ASIC
(ICU)
74
IN
Auto feed signal/Handshake
signal in the reverse
mode/Command data
identification signal
nAutoFd3
ASIC
(ICU)
48
IN
Auto feed signal/Handshake
signal in the reverse
mode/Command data
identification signal
nFault1
ASIC
(ICU)
95
OUT
Printer’s communication
request signal to the host
NC
nFault2
ASIC
(ICU)
70
OUT
Printer’s communication
request signal to the host
NC
nFault3
ASIC
(ICU)
46
OUT
Printer’s communication
request signal to the host
NC
nInit1
ASIC
(ICU)
97
IN
Data direction
(reverse/forward) signal
nInit2
ASIC
(ICU)
71
IN
Data direction
(reverse/forward) signal
nlint3
ASIC
(ICU)
47
IN
Data direction
(reverse/forward) signal
NC
NM-
CPU
82
IN
Pull up
nSelectIn1
ASIC
(ICU)
94
IN
LOW when in the
compatible mode
nSelectIn2
ASIC
(ICU)
69
IN
LOW when in the
compatible mode
nSelectIn3
ASIC
(ICU)
45
IN
LOW when in the
compatible mode
NStrobe1
ASIC
(ICU)
118
IN
LOW during forward data
transmission (Indicates that
the transmitted data are
effective.)
nStrobe2
ASIC
(ICU)
93
IN
LOW during forward data
transmission (Indicates that
the transmitted data are
effective.)
nStrobe3
ASIC
(ICU)
68
IN
LOW during forward data
transmission (Indicates that
the transmitted data are
effective.)
OE
ASIC
63
OUT
DRAM (page memory) read
enable signal
Signal
name
Device
Pin
No.
Input/
Output
Content
Remark
OP_CLK
CPU
63
OUT
Clock signal to the operation
panel
OP_DATA
CPU
59
OUT
Data signal to the operation
panel
OP_KIN1
CPU
70
IN
Key input 1
OP_KIN2
CPU
71
IN
Key input 2
OP_LATCH
ASIC
199
OUT
Panel data latch signal
OP_PSW
CPU
69
IN
PRINT SWITCH
OP_RXD
CPU
61
OUT
Operation panel reception
buffer
NC
OPIRQ-
CPU
30
IN
Operation panel
NC
OSCSEL
ASIC
(ICU)
141
IN
Fixed. (HIGH)
OUTD0
ASIC
65
OUT
(NC)
OUTD1
ASIC
66
OUT
(NC)
OUTD10
ASIC
78
OUT
(NC)
OUTD11
ASIC
77
OUT
(NC)
OUTD12
ASIC
79
OUT
(NC)
OUTD13
ASIC
80
OUT
(NC)
OUTD14
ASIC
81
OUT
(NC)
OUTD15
ASIC
82
OUT
(NC)
OUTD2
ASIC
67
OUT
(NC)
OUTD3
ASIC
68
OUT
((NC)
OUTD4
ASIC
70
OUT
(NC)
OUTD5
ASIC
71
OUT
(NC)
OUTD6
ASIC
73
OUT
(NC)
OUTD7
ASIC
74
OUT
(NC)
OUTD8
ASIC
75
OUT
(NC)
OUTD9
ASIC
76
OUT
(NC)
PARAD0
ASIC
102
IN/OUT (NC)
PARAD1
ASIC
103
IN/OUT (NC)
PARAD2
ASIC
104
IN/OUT (NC)
PARAD3
ASIC
105
IN/OUT (NC)
PARAD4
ASIC
106
IN/OUT (NC)
PARAD5
ASIC
107
IN/OUT (NC)
PARAD6
ASIC
109
IN/OUT (NC)
PARAD7
ASIC
110
IN/OUT (NC)
PCLACK
ASIC
86
IN
(NC)
PCLCS
ASIC
87
IN
(NC)
PCLPRD
ASIC
84
IN
(NC)
PCLREQ
ASIC
85
OUT
(NC)
PE
ASIC
119
OUT
(NC)
PEMP
CPU
32
IN
Paper empty sensor
PError1
ASIC
(ICU)
100
OUT
Identification signal of nInit
signal which shows data
direction (reverse/forward)
PError2
ASIC
(ICU)
76
OUT
Identification signal of nInit
signal which shows data
direction (reverse/forward)
PError3
ASIC
(ICU)
52
OUT
Identification signal of nInit
signal which shows data
direction (reverse/forward)
PFCLK
ASIC
125
IN
Write clock
PIN-
CPU
97
IN
Paper feed sensor
PMCLK
CPU
75
OUT
Polygon motor clock signal
PMD-
ASIC
217
OUT
Polygon motor drive signal
POUT-
CPU
98
IN
Paper exit sensor
PR
ASIC
221
OUT
Power relay control
PRSTART
ASIC
2
IN
Print start trigger signal
PRSTART-
ASIC
209
OUT
Print start signal
PRSTT
ASIC
207
OUT
Pritn start
PRSTT
ASIC
(ICU)
3
IN
Print start
PSIZE
CPU
127
IN
Paper size sensor
PUS
ASIC
228
OUT
Pickup solenoid
PWMCL
CPU
74
OUT
Copy lamp PWM control
NC
PWMSIN
CPU
73
OUT
Sine waveform overlapping
MC
11 – 4
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Sharp AL-840 (serv.man10) Service Manual ▷ Download

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  • Here you can View online or download the Service Manual for the Sharp AL-840 (serv.man10) in PDF for free, which will help you to disassemble, recover, fix and repair Sharp AL-840 (serv.man10) Copying Equipment. Information contained in Sharp AL-840 (serv.man10) Service Manual (repair manual) includes:
  • Disassembly, troubleshooting, maintenance, adjustment, installation and setup instructions.
  • Schematics, Circuit, Wiring and Block diagrams.
  • Printed wiring boards (PWB) and printed circuit boards (PCB).
  • Exploded View and Parts List.