Sharp ER-A220 (serv.man2) Service Manual ▷ View online
Pin
No.
SYMBOL
SIGNAL
NAME
In/Out
Function
39
CLKOUT
/RDY
In
VCC
40
ALE
NC
Out
NOT USE
41
/HOLD
/HOLD
In
Controled by P71
42
/HLDA
NC
Out
NOT USE
43
CBCLK
NC
Out
NOT USE
44
/RD
/RD
Out
Read
45
/BHE
NC
Out
NOT USE
46
/WR
/WR
Out
Write
47
/CS3
CS3
Out
Display segment latch
48
/CS2
/RAS1
Out
Chip select :for RAM
49
/CS1
BUSY
In
FMC :Busy
50
/CS0
/ROS1
Out
Chip select :for ROM
51
A19
NC
Out
NOT USE
52
A18
NC
Out
NOT USE
53
A17
A17
Out
Address bus :17
54
A16
A16
Out
Address bus :16
55
A15
A15
Out
Address bus :15
56
A14
A14
Out
Address bus :14
57
A13
A13
Out
Address bus :13
58
A12
A12
Out
Address bus :12
59
A11
A11
Out
Address bus :11
60
A10
A10
Out
Address bus :10
61
A9
A9
Out
Address bus :9
62
VCC
VDD
In
VDD
63
A8
A8
Out
Address bus :8
64
VSS
GND
In
GND
65
A7
A7
Out
Address bus :7
66
A6
A6
Out
Address bus :6
67
A5
A5
Out
Address bus :5
68
A4
A4
Out
Address bus :4
69
A3
A3
Out
Address bus :3
70
A2
A2
Out
Address bus :2
71
A1
A1
Out
Address bus :1
72
A0
A0
Out
Address bus :0
73
D15
PH4
Out
Paper feed motor :Phalse4
74
D14
PH3
Out
Paper feed motor :Phalse3
75
D13
PH2
Out
Paper feed motor :Phalse2
76
D12
PH1
Out
Paper feed motor :Phalse1
77
D11
P13
Out
Key/Display :Strobe3
78
D10
P12
Out
Key/Display :Strobe2
79
D9
P11
Out
Key/Display :Strobe1
80
D8
P10
Out
Key/Display :Strobe0
81
D7
D7
InOut Data bus :7
82
D6
D6
InOut Data bus :6
83
D5
D5
InOut Data bus :5
84
D4
D4
InOut Data bus :4
85
D3
D3
InOut Data bus :3
86
D2
D2
InOut Data bus :2
87
D1
D1
InOut Data bus :1
88
D0
D0
InOut Data bus :0
89
AN7
DTS
Out
Printer head drive
90
AN6
LATCH
Out
Printer data latch
91
AN5
P105
Out
Printer head voltage ON
92
AN4
P104
Out
CG ROM Bank
93
AN3
P103
In
Head rank
94
AN2
Vref
In
Base voltage :2.495V
95
AN1
P101
In
Printer head voltage check
96
AVSS
GND
In
GND
97
AN0
TH
In
Print head temperature check
98
VREF
VDD
In
VDD
99
AVCC
VDD
In
VDD
100 SIN4
P97
In
Key return :7
3. Clock generator
1) CPU
Two oscillators are connected to the CPU.
The basic clock X3 is supplied from a 12MHz oscillator.
The 12Mhz basic clocks are formed by X3 and W42C21 and inputted
to the Xin pin of the CPU.
to the Xin pin of the CPU.
If the CPU was not operating properly, the signal does not appear on
this line in most cases.
The sub-clock X1 generates 32.768KHz which is primarily used to
update the internal RTC (real time clock).
During the standby mode, it keeps oscillating to update the clock and
monitoring the power recov-ery.
4. Reset circuit
When the mode switch is placed in the "SRV" position, the reset signal
is sent to the CPU to reset the hardware.
is sent to the CPU to reset the hardware.
11
10
27P
C135
CPU
XIN
X3
12MHz
X1
32.768KHz
32.768KHz
12
18P
C134
14
XOUT
XCOUT
XCIN
R110
330
330
W42C3103G
IC9
R109
0
0
CPU
R47
/RESET
C14
C104
MODE SWITCH
SRV' position
SRV' position
VDD
11
+
5. P-OFF circuit
The P-OFF signal detects two signals by two comparators and sent to
the CPU.
+24V signal : When the mode switch is placed in the OFF position,
the P-OFF output from the comparator: IC10A becomes
low to turn the power off.
When the mode switch is in positions other than OFF,
the P-OFF output from the comparator:IC10A becomes
high to turn the power on.
high to turn the power on.
VCC signal : Though the MODE switch is at ON position, if the logic
power voltage Vcc falls below the specified level, the
P-OFF signal is driven to LOW by the comparator
IC10B.
IC10B.
6. Memory circuit
1) Address map
EP-ROM :
Not available as standard equipment. The EP-ROM
socket is provided for rewriting the program for the CPU
internal FLASH-ROM.
2) RAM control
3) EP-ROM (IPL ROM) control
IC2 : EP-ROM (IPL ROM) is used to write data onto the CPU internal
FLASH-ROM.
+24V
VCC
+24V
VCC
R119
56K
R128
2.7K
2.7K
3
2
1
8
4
IC10A
BA10393
5
6
7
8
4
IC10B
BA10393
R121
2.4KF
2.4KF
R122
13KF
13KF
D101
1SS353
P-OFF
C137
0.47uF
0.47uF
C138
0.47uF
0.47uF
C147
0.1uF
R120
3KF
R123
2.7KF
VREF
(2.495V)
(2.495V)
P-OFF
19
Segment latch address
00000h
00400h
05400h
06000h
08000h
40000h
28000h
C0000h
FFFFFh
CPU internal RAM
20kbytes
External S-RAM : 128kbytes
(128kbytes area)
EP-ROM(For IPL) : 256k bytes
(512kbytes area)
CPU internal FLASH-ROM
256kbytes
/CS0 area
30000h - BFFFFh
*30000h - 3FFFFh :
Not used
30000h - BFFFFh
*30000h - 3FFFFh :
Not used
/CS2 area
08000h - 27FFFh
08000h - 27FFFh
/CS3 area
06000h - 07FFFh
06000h - 07FFFh
CPU
S-RAM
128K byte
IC3B
A0-A16
D0-7
A0-A16
A0-A16
D0-7
I/O0-7
/CS2
/CS2
/CE
/RD
/RD
/WR
/WE
/WR
/OE
Power supply circuit
or
NI-MH battery
VDD
VCC
VDD
VCC
VCC
CPU
IC5B
P71
/HOLD
IC5B
VCC
/CS0
/OE
D0-D7
A0-A17
VCC
SHORT PIN
CNVss
SP1
IC2
EP-ROM
(IPL ROM)
D0-D7
A0-A17
/RD
7. Printer control circuit
1) Paper feed motor circuit
A pulse motor is used as the paper feed motor.
Drive sequence of the pulse motor is as follows:
SEQUENCE
SIGNAL
A
/A
B
/B
STEP1
High
Low
Low
High
STEP2
High
Low
High
Low
STEP3
Low
High
High
Low
STEP4
Low
High
Low
High
2) Print circuit
Thermal head configuration
As shown in the equivalent circuit in the figure, thermal head con-
sists of heating elements and head drivers which drives and con-
trols those heating elements.
The serial print data input through the DATA IN (D1) is transferred
to the shift register synchronizing with the CLOCK (CP) and stored
to the shift register synchronizing with the CLOCK (CP) and stored
in the latch register by the LATCH (LA) signal.
The head conduction signals (print commands 1 ~ 6) turn the gate
on to conduct the heating element corresponding to the print data.
Equivalent circuit of thermal head
Head splitting
The thermal head has 6 strobes so that it is possible to print
dividing up to 6 times. The relationship between the strobes and
dividing up to 6 times. The relationship between the strobes and
heating elements is shown below.
Strobe terminals and conduction heating elements
STB No.
Heating element No.
Number of dots/STB
1
1 ~ 64
64
2
65 ~ 128
64
3
129 ~ 192
64
4
193 ~ 256
64
5
257 ~ 320
64
6
321 ~ 384
64
Print data and printing position
384-bit data No.1 ~ 384 transferred by the DTA IN (DI) are printed
in the position shown in the figure.
CPU
74HC32
VH-
VH-
/A
A
B
PH1
PH3
PH2
PH4
/B
To Papper feed motor
LB1843V
74HC123D
LB1843V
STB6
23
VH
1,2,3,26,27,28 dot 384
L-GND
18
P-GND
13,14,15,16,17
STB5
22
STB4
21
STB3
10
STB2
9
STB1
8
/LATCH
5
DATA IN
25
CLOCK
6
DATA OUT
4
VDD
7
NC
19,20,21
TM
11
TM
12
dot 1
6
5
4
3
2
1
Heating element
Latch register
Shift register
Thermister
STB terminal is pulled down inside the IC.
DATA IN
1 2 3 4 ..........................383 384
Paper feed direction
Record paper
Print surface
Data
Printer mechanism
Motor
Print data and printing position
8. Paper take up motor drive circuit
When the MOTOR signal from the CPU is HIGH, Q1 is turned on to
operate the motor.
9. Drawer drive circuit
When the P60 signal from the CPU is HIGH, Q9 is turned on to
operate the solenoid.
10. Buzzer drive circuit
When the BUZ1 signal from the CPU is HIGH, Q6 is turned on to
operate the buzzer.
operate the buzzer.
11. Keyboard circuit
Four P10-13 signals from the CPU are converted into 16 strobe signals by two 74HC138 for use in various functions.
CPU
TA4IN/U
VLED
MOTOR
M
Q1
R46
R45
CN3
D115
CPU
/RST0
+24V
P60
Q9
R164
R163
CN6
C161
ICP103
1.0A
Micro Switch
Drawer
solenoid
C162
CPU
TA4OUT/U
VCC
BUZ1
BZ1
BZ
D7
Q3
CPU
P10-13
P92-97
Key
Matrix
Head up
sensor
HC138
P10-13
P10-13
/S8-9
/S0-7
/S0-9
P92-97
Mode
Switch
/S0-7
/S0-9
P91
Paper
feed key
/S1
Receipt
near end
sensor
/S3
/S4
RS232
/CI
signal
/S9
P91
Front
display
74HC374
a,b,c,d,e,f,g,dp
/CS3
Pop-up
display
G1',G2',
G3'G4',G5',
G6',PDSG7
(PDSG7:G7')
G3'G4',G5',
G6',PDSG7
(PDSG7:G7')
/S0 - 9
A',B',C',D',E',F',G',DP'
D0-7
D0-7
/CS3
P90
HC138
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