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Pin No.

Terminal name

I/O

Operation function

1

DIN1

I

Amplifier built-in data input terminal (coaxial, corresponding to optical module)

2

DIN2

I

Data input terminal (corresponding to optical module)

3

E/DOUT

O

Emphasis, input biphase, validity flag output terminal

4

VDD

Power

5

R

I

VCO gain control input terminal

6

VIN

I

VCO free run setting input terminal

7

VCO

O

LPF setting terminal of PLL

8

GND

Grounding

9

CKSEL

I

System clock selection input terminal

10

XMODE

I

Reset input terminal

11

AVOCK

I

PLL erroneous lock prevention clock input terminal

12

TEST1

I

Test input terminal (to be grounded usually)

13

TEST2

I

Test input terminal (to be grounded usually)

14

SCLK/CL

I

Microcomputer IF Clock input terminal

15

XLAT/CE

I

Microcomputer IF latch/chip enable input terminal

16

SWDT/DI

I

Microcomputer IF write data input terminal

17

SRDT/DO

O

Microcomputer IF read data output terminal

18

DQSY/LD

O

Microcomputer IF Sub-Q sync and ID sync output terminal

19

CKOUT

O

VCO clock output terminal (Self-run oscillation 384fs, 512fs)

20

FS128

O

128fs clock output terminal

21

BCK

O

Bit clock output terminal

22

LRCK

O

L/R clock output terminal (L-ch=H, R-ch=L)

23

DATAOUT

O

Audio data output terminal

24

ERROR

O

PLL lock error mute output terminal

Microcomputer interface

C-Bit detection

Input

section

Data

demodulator

Lock error detection

Mute output

Timing

PLL

TEST

Sub-Q detection

SCLK/CL

14

15

16

1

2

3

XLAT/CE

SWDT/DI

DIN1

DIN2

E/DOUT

CKSEL

AVOCK

R

VIN

VCO

DQSY/LD

SRDT/DO

ERROR

DATAOUT

SFS128

LRCK

BCK

CKOUT

TEST1

TEST21

XMODE

9

5

6

7

11

18

17

24

23

20

22

21

19

12

13

10

VA—Analog Positive Supply: Pin 34

Analog positive supply for clock generator. Nominally +3.3 V.

AGND—Analog Supply Ground: Pin 35

Analog ground for clock generator PLL.

VD1, VD2, VD3—Digital Positive Supply: Pins 1, 12, 23

Digital positive supplies. Nominally +2.5 V.

DGND1, DGND2, DGND3—Digital Supply Ground: Pins 2, 13, 24

Digital ground.

FILT1—Phase-Locked Loop Filter: Pin 33

Connects to an external filter for the on-chip phase-locked loop. This pin does not meet Cirrus Logic's ESD tolerance of 2000V

using the human body model. This pin will tolerate ESD of 1000V using the human body model.

FILT2—Phase Locked Loop Filter: Pin 32

Connects to an external filter for the on-chip phase-locked loop. This pin does not meet Cirrus Logic's ESD tolerane of 2000V

using the human body model. This pin will tolerate ESD of 1000V using the human body model.

CLKIN—Master Clock Input: Pin 30

CS493XX clock input. When in internal clock mode (CLKSEL=DGND), this input is connected to the internal Pll from which all internal

clocks

are derived. When in external clock mode (CLKSEL=VD), this input is connected to the DSP clock.

CLKSEL—DSP Clock Select: Pin 31

This pin selects the clock mode of the CS493XX. When CLKSEL is low, CLKIN is connected to the internal PLL from which all internal
clocks are derived. When CLKSEL is high CLKIN is connected to the DSP clock.

DATA7, EMAD7, GPIO7 — Pin8
DATA6, EMAD6, GPIO6 — Pin9
DATA5, EMAD5, GPIO5 — Pin10
DATA4, EMAD4, GPIO4 — Pin11
DATA3, EMAD3, GPIO3 — Pin14
DATA2, EMAD2, GPIO2 — Pin15
DATA1, EMAD1, GPIO1 — Pin16
DATA0, EMAD0, GPIO0 — Pin17

In parallel host mode, these pins provide a bidirectional data bus. If a serial host mode is selected, these pins can provide a multiplexed
address and data bus for connecting an 8-bit external memory. Otherwise, in serial host mode, these pins can act as general-purpose
input or output pins that can be individually configured and controlled by the DSP.

A0, SCCLK—Host Parallel Address Bit Zero or Serial Control Port Clock: Pin 7

In parallel host mode, this pin serves as one of two address input pins used to select one of four parallel registers. In serial host mode,
this pin serves as the serial control clock signal, specifically as the SPI clock input or the I

2

C clock input.

A1, SCDIN—Host Address Bit One or SPI Serial Control Data Input: Pin 6

In parallel host mode, this pin seves as on of two address input pins used to select one of four parallel registers. In SPI serial host mode,
this pin serves as the data input.

RD, R/W, EMOE, GPIO11—Host Parallel Output Enable or Host Parallel R/W or External Memory Output Enable or General Purpose

Input & Output Number 11: Pin 5

In Intel parallel host mode, this pin serves as the active-low data bus enable input. In Motorola parallel host mode, this pin serves as the
read-high/write-low control input signal. In serial host mode, this pin can serve as the external memory active-low data-enable output
signal. Also in serial host mode, this pin can serve as a general purpose input or output bit.

WR, DS, EMWR, GPIO10—Host Write Strobe or Host Data Strobe or External Memory Write Enable or General Purpose Input &

Output Number 10: Pin 4

In Intel parallel host mode, this pin serves as the active-low data-write-input strobe. In Motorola parallel host mode, this pin serves as the
active-low data-strobe-input signal. In serial host mode, this pin can serve as the external-memory active-low write-enable output signal.
Also in serial host mode, this pin can serve as a general purpose input or output bit.

CS—Host Parallel Chip Select, Host Serial SPI Chip Select: Pin 18

In parallel host mode, this pin serves as the active-low chip-select input signal. In serial host SPI mode, this pin is used as the active-low
chip-select input signal.

RESET—Master Reset Input: Pin 36

Asynchronous active-low master reset input. Reset should be low at power-up to initialize the CS493XX and to guarantee that the device
is not active during initial power-on stabilization periods. At the rising edge of reset the host interface mode is selected contingent on the
state of the RD, WR and PSEL pins. Additionally, an autoboot sequence can be initiated if a serial control mode is selected and ABOOT
is held low. If reset is low all bidirectional pins are high impedance inputs.

SCDIO, SCDOUT, PSEL, GPIO9—Serial Control Port Data Input and Output, Parallel Port Type Select: Pin 19

In I

2

C mode, this pin serves as the open-drain bidirectional data pin. In SPI mode this pin serves as the data output pin. In parallel host

mode, this pin is sampled at the rising edge of RESET to configure the parallel host mode as an Intel type bus or as a Motorola type bus.
In Parallel host mode, after the bus mode has been selected, the pin can function as a general-purpose input or output pin.

EXTMEM, GPIO8—External Memory Chip Select or General Purpose Input & Output Number 8: Pin 21

In serial control port mode, this pin can serve as an output to provide the chip-select for an external byte-wide ROM. In parallel and serial
host mode, this pin can also function as a general-purpose input or output pin.

INTREQ, ABOOT—Control Port Interrupt Request, Automatic Boot Enable: Pin 20

Open-drain interrupt-request output. This pin is driven low to indicate that the DSP has outgoing control data and should be serviced by
the host. Also in serial host mode, this siganl intiates an automatic boot cycle from external memory if it is held low through the rising edge
of reset.

AUDATA2—Digital Audio Output 2: Pin 39

PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCM output defaults to DGND as output until
enabled by the DSP software.

AUDATA1—Digital Audio Output 1: Pin 40

PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCM output defaults to DGND as output until
enabled by the DSP software.

AUDATA0—Digital Audio Output 0: Pin 41

PCM multi-format digital-audio data output, capable of two-, four-, or six-channel 20-bit output. This PCM output defaults to DGND as
output until enabled by the DSP software.

MCLK—Audio Master Clock: Pin 44

Bidirectional master audio clock. MCLK can be an output from the CS493XX that provides an oversampled audio- output clock at either
128 Fs, 256 Fs, or 512 Fs. MCLK can be an input at 128 Fs, 256 Fs, 384 Fs, or 512 Fs. MCLK is used to derive SCLK and LRCLK when
SCLK and LRCKL are driven by the CS493XX.

SCLK—Audio Output Bit Clock: Pin 43

Bidirectional digital-audio output bit clock. SCLK can be an output that is dirived from MCLK to provide 32 Fs, 64 Fs,128Fs, 256 Fs, or
512 Fs, depending on the MCLK rate and the digital-output configuration. SCLK can also be an input and must be at least 48Fs or greater.

LRCLK—Audio Output Sample Rate Clock: Pin 42

Bidirectional digital-audio output-sample-rate clock. LRCLK can be an output that is divided from MCLK to provide the output sample rate
depending on the output configuration. LRCLK can also be an input. AS an input LRCLK is independent of MCLK.

XMT958—SPDIF Transmitter Output: Pin 3

CMOS level output that contains a biphase-encoded clock for synchronously providing two channels of PCM digital audio or a IEC61937
compressed-data interface or both. This output typically connects to the input of an RS-422 transmitter or to the input of an optical
transmitter.

SCLKN1, STCCLK2—PCM Audio Input Bit Clock: Pin 25

Bidirectional digital-audio bit clock that is an output in master mode and an input in slave mode. In slave mode, SCLKN1 operates
asynchronously from all other CS493XX clocks. In master mode, SCLKN1 is derived from the CS493XX internal clock generator. In either
master or slave mode, the active edge of SCLKN1 can be programmed by the DSP. For applications supporting PES layer synchronization
this pin can be used as STCCLK2, which provides a path to the internal STC 33 bit counter.

LRCLKN1—PCM Audio Input Sample Rate Clock: Pin 26

Bidirectional digital-audio frame clock that is an output in master mode and an input slave mode. LRCLKN1 typically is run at the sampling
frequency. In slave mode, LRCLKN1 operates asynchronously from all other CS493XX clocks. In master mode, LRCLKN1 is derived from
the CS493XX internal clock generator. In either master or slave mode, the polarity of LRCLKN1 for a particular subframe can be
programmed by the DSP.

SDATAN1—PCM Audio Data Input Number One: Pin 22

Digital-audio data input that can accept from one to six channels of compressed or PCM data. SDATAN1 can be sampled with either edge
of SCLKN1, depending on how SCLKN1 has been configured.

CMPCLK, SCLKN2—PCM Audio Input Bit Clock: Pin 28

Bidirectional digital-audio bit clock taht is an output in master mode and an input in slave mode. In slave mode, SCLKN2 operates
asynchronously from all other CS493XX clocks. In master mode, SCLKN2 is derived from the CS493XX internal clock generator. In either
master or slave mode, the active edge of SCLKN2 can be programmed by the DSP. If the CDI is configured for bursty delivery, CMPCLK
is an input used to sample CMPDAT.

CMPREQ, LRCLKN2—PCM Audio Input Sample Rate Clock: Pin 29

When the CDI is configured as a digital audio input, this pin serves as a bidirectional digital-audio frame clock that is an output in master
mode and an input in slave mode. LRCLKN2 typically is run at the sampling frequency. In slave mode, LRCLKN2 operates asynchronously
from all other CS493XX clocks. In master mode, LRCLKN2 is derived from the CS493XX internal clock generator. In either master or slave
mode, the polarity of LRCLKN2 for a particular subframe can be programmed by the DSP. When the CDI is configured for bursty delivery,
or parallel audio data delivery is being used, CMPREQ is an output which serves as an internal FIFO monitor. CMPREQ is an active low
signal that indicates when another block of data can be accepted.

CMPDAT, SDATAN2—PCM Audio Data Input Number Two: Pin 27

Digital-audio data input that can accept from one to six channels of compressed or PCM data. SDATAN2 can be sampled with either edge
of SCLKN2, depending on how SCLKN2 has been configured. Similarly CMPDAT is the compressed data input pin when the CDI is
configured for bursty delivery. When in this mode, the CS493XX internal PLL is driven by the clock recovered from the incoming data
stream.

DC—Reserved: Pin 38

This pin is reserved and should be pulled up with an external 4.7k resistor.

DD—Reserved: Pin 37

This pin is reserved and should be pulled up with an external 4.7k resistor.

PIN No.

PIN NAME

I/O ATTR

I/O CELL

PDV CELL

LIO CELL

1

VDD

P

VDD

*

*

2

HADR0

I

IDC

*

*

3

HADR1

I

IDC

*

*

4

HADR2

I

IDC

*

*

5

HCS

I

IDC

*

*

6

HWR

I

IDC

*

*

7

HRD

I

IDC

*

*

8

HDAT0

B

BDC3

PDV2T

*

9

HDAT1

B

BDC3

PDV2T

*

10

HDAT2

B

BDC3

PDV2T

*

11

HDAT3

B

BDC3

PDV2T

*

12

HDAT4

B

BDC3

PDV2T

*

13

HDAT5

B

BDC3

PDV2T

*

14

HDAT6

B

BDC3

PDV2T

*

15

HDAT7

B

BDC3

PDV2T

*

16

VSS

P

VSS

PDV2T

*

6

VD1

DGND1

AUDATA3, XMT958

WR, DS EMWR, GPIO10

RD, R/W, EMOE, GPIO11

A1, SCDIN

A0, SCCLK

DATA7, EMAD7, GPIO7

DATA6, EMAD6, GPIO6

DATA5, EMAD5, GPIO5

DATA4, EMAD4, GPIO4

VD2

DGND2

DATA3, EMAD3, GPIO3

DATA2, EMAD2, GPIO2

DATA1, EMAD1, GPIO1

DATA0, EMAD0, GPIO0

CS

SCDIO,SCDOUT, PSEL, GPIO9

ABOOT, INTREQ

EXTMEM, GPIO8

SDATAN1

7
8
9

10

11
12

CS493XX-CL

44-Pin PLCC

Top View

13
14
15
16
17

18 19 20 21 22 23 24 25 26 27 28

29

30

31

32

33

34

35

36

37

38

39

5 4 3 2 1 44 43 42 41 40

MCLK

SCLK

LRCLK

AUDATA0

AUDATA1

AUDATA2

DC

DD

RESET

AGND

VA

FILT1

FILT2

CLKSEL

CLKIN

CMPREQ, LRCLKN2

CMPCLK, SCLKN2

CMPDAT,  SDATAN2, RCV958

LRCLKN1

SCLKN1,STCCLK2

DGND3

VD3

Pin No.

Pin Name

2,3,4,5-12,23,25,

A0~A16

Addresses

26,27,28,29

13-15,17-24

O0~O7

Outputs

22

CE

Chip Enable

24

OE

Output Enable

31

PGM

Program Strobe

30

NC

No Connect

32

Vcc

1

Vpp

16

GND

Function

Vcc

GND

VPP

OE

CE

PGM

A0~A16

ADDRESS

INPUTS

OE, CE AND

PROGRAM LOGIC

Y DECODER

X DECODER

OUTPUT

BUFFERS

Y-GATING

CELL MATRIX

IDENTIFICATION

DATA OUTPUTS

O0~O7