Sharp DV-600H (serv.man2) Service Manual ▷ View online
DV-600S
DV-600H
DV-600H
Pin No.
Terminal name
I/O
Operation function
Remarks
44
TRO
O
Tracking equalizer output terminal.
45
VREF
–
Analog reference power terminal.
46
RFGC
O
RF amplitude adjustment control signal output terminal.
Output of 3-pole PWM signal. (PWM carrier = 88.2 kHz)
Output of 3-pole PWM signal. (PWM carrier = 88.2 kHz)
47
TEBC
O
Tracking balance control signal output terminal.
Output of 3-pole PWM signal. (PWM carrier = 88.2 kHz)
Output of 3-pole PWM signal. (PWM carrier = 88.2 kHz)
48
FMO
O
Feed equalizer output terminal.
Output of 3-pole PWM signal. (PWM carrier = 88.2 kHz)
Output of 3-pole PWM signal. (PWM carrier = 88.2 kHz)
49
FVO
O
Speed error signal or feed search EQ output terminal.
Output of 3-pole PWM signal. (PWM carrier = 88.2 kHz)
Output of 3-pole PWM signal. (PWM carrier = 88.2 kHz)
50
DMO
O
Disc equalizer output terminal.
Output of 3-pole PWM signal. (PWM carrier = DSP system
88.2kHz, to be synchronized with PXO)
Output of 3-pole PWM signal. (PWM carrier = DSP system
88.2kHz, to be synchronized with PXO)
51
2VREF
–
52
SEL
O
53
/FOON
O
54
/DFCT
O
55
/SRCH
O
56
/SHC
O
57
VDD
–
58
VSS
–
59
IO0
I/O
General use I/O port.
60
IO1
It is possible to select the input port and output port according
to command.
to command.
61
IO2
In case of input port the terminal state (H/L) can be read with
the read command.
the read command.
62
IO3
In case of output port the terminal state (H/L/HiZ) can be
controlled with the command.
controlled with the command.
63
/DMOUT
Terminal to set the mode to output dual value PWM of feed
equalizer from the IO0,1 terminal and to output the dual value
PWM from disc equalizer of IO2,3 terminal “L” Active.
equalizer from the IO0,1 terminal and to output the dual value
PWM from disc equalizer of IO2,3 terminal “L” Active.
64
/CKSE
X’tal selection terminal.
When 16.9344 MHz: “H” When 33.8688 MHz: “L”
When 16.9344 MHz: “H” When 33.8688 MHz: “L”
65
/DACT
Test terminal.
66
TESIN
Test input terminal.
67
TESIO1
Test input/output terminal.
68
VSS
Digital ground terminal.
69
PXI
DSP system clock oscillation circuit input terminal.
70
PXO
DSP system clock oscillation circuit output terminal.
71
VDD
Digital + power terminal.
72
XVSS
Ground terminal for system clock oscillation circuit.
73
XI
System clock oscillation circuit input terminal.
74
XO
System clock oscillation circuit output terminal.
75
XVDD
Positive power terminal for system clock oscillation circuit.
76
DVDD
–
D/A converting section power terminal.
77
RO
O
R channel data forward rotation output terminal.
78
DVSS
–
D/A converting section analog ground terminal.
79
DVR
–
D/A converting section reference voltage terminal.
80
LO
O
L channel data forward rotation output terminal.
81
DVDD
–
D/A converting section power terminal.
82
TEST1
I
Test terminal.
Pull-up resistor
To be opened usually.
built in.
83
TEST2
I
Test terminal.
Pull-up resistor
To be opened usually.
built in.
84
TEST3
I
Test terminal.
Pull-up resistor
To be opened usually.
built in.
85
BUS0
I/O
Microcomputer interface data input/output terminal.
Schmidt input
86
BUS1
I/O
CMOS port
87
BUS2
I/O
11-20
DV-600S
DV-600H
DV-600H
Pin No.
Terminal name
I/O
Operation function
Remarks
88
BUS3
I/O
89
VDD
–
Digital + power terminal.
90
VSS
–
Digital ground terminal.
91
BUCK
I
Microcomputer interface clock input terminal.
Schmidt input
92
/CCE
I
Microcomputer interface chip enable signal input terminal.
Schmidt input
BUS0 to 3 is active in “L” state.
93
TEST4
I
Test terminal.
Pull-up resistor
To be opened usually.
built in.
94
/TEMOD
I
Local test mode selection terminal.
Pull-up resistor
built in.
built in.
95
/RST
I
Reset signal input terminal.
Pull-up resistor
Reset state: “L”
built in.
96
TEST0
I
Test terminal.
Pull-up resistor
To be opened usually.
built in.
97
/HSO
O
Playback speed mode flag output terminal.
98
/UHSO
O
99
EMPH
O
Subcode Q data emphasis flag output terminal.
Emphasis ON: “H” OFF: “L”
Output polarity can be inverted by the command.
Emphasis ON: “H” OFF: “L”
Output polarity can be inverted by the command.
100
LRCK
O
Channel clock (44.1 kHz) output terminal.
L channel “L” R channel: “H”
Output polarity can be inverted by the command.
L channel “L” R channel: “H”
Output polarity can be inverted by the command.
/UHSO
/HSO
Playback speed
H
H
x1 speed playback
H
L
x2 speed playback
L
H
x4 speed playback
L
L
x8 speed playback
• Block Diagram
76
DVDD
77
RO
78
DVSS
79
DVR
80
LO
81
DVDD
82
TEST1
83
TEST2
84
TEST3
85
BUS0
86
BUS1
87
BUS2
88
BUS3
89
VDD
90
VSS
91
BUCK
92
/CCE
93
TEST4
94
/TEMOD
95
/RST
96
TEST0
97
/HSO
98
/UHSO
99
EMPH
100
LRCX
50 DMO
49 FVO
48 FMO
47 TEBC
46 RFGC
45 VREF
44 TRO
43 FOO
42 TEZI
41 TEIN
40 TSIN
39 SBAD
38 FEIN
37 RFRP
36 RFZI
35 RFCT
34 AVDD
33 RFIN
32 SLCO
31 AVSS
30 VCOF
29 VCOREF
28 PVREF
27 LPFO
26 LPFN
1
2
3
4
VSS
BCK
AOUT
5
6
7
8
MBOB
IPF
SBOK
CLCK
9 10 11 12
VDD
VSS
DATA
13
SBSY
14
SPCK
15
SPDA
16
COFS
17
MONIT
18
VDD
19
TESIO0
20
P2VREF
21
SPDO
22
PDOS
23
PDO
24
XMAXS
25
TMAX
SFSY
DOUT
75 74 73 72
XVDD
XO
XI
71 70 69 68
VDD
PXO
PXI
VSS
67 66 65 64
TESIO1
TESIN
/DACT
63
/DMOUT
62
IO3
61
IO2
60
IO1
59
IO0
58
VSS
57
VDD
56
/SHC
55
/SRCH
54
/DFCT
53
/FOON
52
SEL
51
2VREF
/CKSE
XVSS
LPF
1Bit
DAC
ROM
RAM
1Gk RAM
PWM
D/A
A/D
CLV servo
PWM
VCO
PLL TMAX
+
–
–
+
–
–
+
–
–
+
–
–
Clock
genelator
Servo control
Digital
equalizer
Automatic
adjusting circuit
Micon
inter
face
Digital out
Status
Correction
circuit
Sync signal
protection
EFM
demodulation
Data slicer
Subcode
demodulation
circuit
demodulation
circuit
Audio output
circuit
Address circuit
11-21
DV-600S
DV-600H
DV-600H
Pin No.
Terminal name
I/O
Operation function
1
LRCIN
I
LRCK clock input (fs)
(3)
2
DIN
I
Data input
(3)
3
BCKI
I
Bit clock input for data.
4
CLKO
O
System clock buffered output.
5
XTI
I
Connection of crystal oscillator or external clock input.
6
XTO
O
Connection of crystal oscillator
7
DGND
–
Digital GND
8
V
DD
–
Digital power +5V
9
V
CC
2R
–
Analog power +5V
10
AGND2R
–
Analog GND
11
EXTR
O
Rch Analog output amp. • common
12
NC
–
Not connected.
13
V
OUT
R
O
Rch Analog voltage output
14
AGND1
–
Analog GND
15
V
CC
1
–
Analog power +5V
16
V
OUT
L
O
Lch Analog voltage output
17
NC
–
Not connected.
18
EXTL
O
Lch Analog output amp. • common
19
AGND2L
–
Analog GND
20
V
CC
2L
–
Analog power +5V
21
ZERO
O
Zero data • flug
22
RSTB
I
Resetting. While this pin is in "L" state, the DF and delta -sigma modulator is in reset state.
(1)
23
CS/IWO
I
Chip selection/input format selection
(2)
24
MODE
I
Mode control selection (H: Software, L: Hardware)
(1)
25
MUTE
I
Mute control
(1)
26
MD/DM0
I
Mode control data/deemphasis selection 1
(1)
27
MC/DM1
I
Mode control BCK/deemphasis selection 2
(2)
28
ML/IIS
I
Mode control latch/input format selection
(1)
Note: (1) Pins 22, 24, 25, 26, 27, and 28: With Schmidt trigger input pull-up resistor (2) Pin 23: With Schmidt trigger input pull-down resistor
(3) Pins 1, 2, and 3: Schmidt trigger input
11-16. IC801 PCM1716E
AUDIO D/A CONVERTER
BCKI
LRCIN
DIN
ML/IIS
MC/DM1
MD/DM0
MD/DM0
CS/IWO
MODE
MUTE
RSTB
Sirial
Input
Input
I/F
Mode
Control
I/F
XTI XTO
CLKO
V
CC
1AGND1
DGND
V
DD
Power
BPZ-Cont.
Crystal OSC
8-time oversampling
digital filter with
function controller
Multilevel
delta/sigma
modulator
DAC
20 19
9
10
DAC
Low-pass
filter
Low-pass
filter
V
OUT
L
V
CC
2L
AGND2L
V
CC
2R
AGND2R
EXTL
EXTR
V
OUT
R
ZERO
Open Drain
16
18
13
11
21
7
8
4
6
5
14
15
22
25
24
23
26
27
28
2
1
3
• Block Diagram
11-22
DV-600S
DV-600H
DV-600H
11-17. IC5001 IMN12510F
FL DRIVER
18
VDD
Power supply terminal
Input
VDD: +5V
±
0.5V
21
VSS
VSS: 0V
16
VPP
FLP driver power
Input
VPP: VDD–35V
The voltage to be supplied to the SEG 0 to 7, DGT 0 to 7 pull-down
resistor is applied.
The voltage to be supplied to the SEG 0 to 7, DGT 0 to 7 pull-down
resistor is applied.
19
OSCI
Clock input
Input
Oscillation input terminal
A terminal to which the ceramic
20
OSCO
Clock output
Oscillation output terminal
oscillation terminal is connected.
To OSCI in case of clock input from outside in case of separate excitation
22
NCS
Chip select input
Input
"L": Serial input allowed
"H": Serial input inhibited
23
SCK
Sirial clock input
Input
Serial transfer clock input
24
SDI
Sirial data input
Input
Sirial data input
The command data, address data, indication data, control register
data, and port output data are input.
The command data, address data, indication data, control register
data, and port output data are input.
25
SDO
Sirial data output
Output
Sirial data output
The key scan input data and port input data are output.
The key scan input data and port input data are output.
26~30
P30~P34
Key scan input
In/Output
There are 5 bits. Bitwise selection of key scan input/general-use
input/general-use output is enabled. The pull-down resistor is pro
vided between this terminal and the VSS terminal.
The general-use output is large current output for LED drive.
input/general-use output is enabled. The pull-down resistor is pro
vided between this terminal and the VSS terminal.
The general-use output is large current output for LED drive.
31~38
SEG0~SEG7
High voltage resistance output
Output
8-bit high voltage resistance output port. (Segment output)
The output type is Pch open drain. The pull-down resistor is built in
between this terminal and the VPP terminal.
The output type is Pch open drain. The pull-down resistor is built in
between this terminal and the VPP terminal.
39~42
P10~P13
High voltage resistance output
Output
4-bit high voltage resistance output port.
SEG8~SEG11
Bitwise selection of general-use output/segment output is enabled.
The output type is Pch open drain.
The output type is Pch open drain.
43, 44
P20~23
High voltage resistance output
In/Output
4-bit high voltage resistance output port.
1, 2
DGT12/SEG15
Bitwise selection of general-use input/general-use output/seg ment
output/digit output is enabled. The output type is Pch open drain.
output/digit output is enabled. The output type is Pch open drain.
DGT15/SEG12
Large current output for LED drive
3~6
P00~P03
High voltage resistance output
Output
4-bit high voltage resistance output port.
DGT8~DGT11
Bitwise selection of general-use output/digit output is enabled.
The output type is Pch open drain.
The output type is Pch open drain.
7~10
DGT0~DGT7
High voltage resistance output
Output
8-bit high voltage resistance output port. (Digit output)
12~15
The output type is Pch open drain. The pull-down resistor is built
in between this terminal and the VPP terminal.
in between this terminal and the VPP terminal.
Terminal Terminal Name
Name
In/Output
Function
~
)
• Block Diagram
11-23
NC S
SC K
SD I
SD O
VP P
VD D
VS S
S C1
S C2
D0
D7D8
(P53)
(P32) (P20)
(P23)
(P13)
(P10)
D11
DS12
DS15
S11
S8 S7
S0
P34
P30
5
8
4
4
4
4
4
4
4
4
4
8
4
Timing generating
circuit
S B ( 8 )
L A T C H ( 8 )
Shift Resistor
MPL
MPL
MPL
LATCH(5)
5 X 1 2
( 8 X 3 2 ) X 2
S E G ( 1 6 )
D G T ( 1 6 )
F L P
K E Y
M A T R I X
Comannding
Decoder
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