Sharp XL-UH4H (serv.man2) Service Manual ▷ View online
XL-UH4H
7 – 9
U2 92L31003980031 : FLASH MEMORY ( SST39VF800A )
Figure 7-7 BLOCK DIAGRAM OF IC
PIN DESCRIPTION
SST39LF / VF800A
A15
A14
A13
A12
A11
A10
A18
A17
A9
A7
A6
A5
A4
A3
A1
A2
A8
NC
NC
NC
NC
NC
NC
WE#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
0E#
CE#
A0
DQ8
DQ0
DQ9
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
NC
V SS
V SS
V DD
Memory Address
Address Buffer & Latches
X-Decoder
SuperFlash
Memory
Y-Decoder
I/O Buffers and Data Latches
DQ
CE#
OE#
WE#
Control Logic
15
DQ
O
-
Symbol
Pin Name
Functions
A
Address Inputs
To provide memory addresses. During Sector-Erase address lines will select the
A
MS
DD
0
1
A
Most significant address
=
MS
A
for SST39LF/VF200A,
=
MS
A
16
for SST39LF/VF400A, and
A
17
for SST39LF/VF800A
A
18
-
-
A
A
MS
11
-
A
A
MS 15
-
sector. During Block-Erase address lines will select the block.
DQ
Data Input/output
To ouput data during Read cycles and receive input data during Write cycles.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
NC
No Connection
Unconnected pins.
WE#
Write Enable
To control the Write operations.
V
Power Supply
To provide power supply voltage:
SS
V
Ground
DQ
15
0
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
The outputs are in tri-state when OE# or CE# is high.
3.0-3.6V for SST39LF200A/400A/800A
2.7-3.6V for SST39VF200A/400A/800A
2.7-3.6V for SST39VF200A/400A/800A
1.
XL-UH4H
7 – 10
IC501 92L31000731400 : VOLUME CONTROLLER ( SC7314 )
Figure 7-8 BLOCK DIAGRAM OF IC
1
V
DD
2
GND
3
L
4
R
5
IN (R)
6
OUT
(R)
7
LOUD (R)
8
R4
9
R3
10
R2
11
R1
12
LOUD (L)
13
L4
14
L3
28
CREF
27
SCL
26
SDA
25
DIF GND
24
OUT
(L)
23
OUT
(R)
22
BOUT
(R)
21
BIN (R)
20
BOUT
(L)
19
BIN (L)
18
OUT
(L)
17
IN (L)
16
L1
15
L2
SC7314
18
OUT
(L)
17
IN
(L)
12
LOUDNESS
(L)
20
B-OUT
(L)
19
B-IN
(L)
3
TREBLE
(L)
6
OUT
(R)
1
8
9
10
11
28
V
DD
2
GND
5
IN
(R)
7
LOUDNESS
(R)
22
13
14
15
16
B-OUT
(R)
21
23 Rout
25 GND
26 SDA
27 SCL
24 Lout
B-IN
(R)
4
TREBLE
(R)
I
2
C BUS Decode + Data Storage Lock
Vol Control
Vcc
C
REF
Input selector
Gain control
Gain control
Input selector
Gain control
Gain control
L
channel input
Bass
Control
Treble
Control
Vol Control
Bass
Control
Treble
Control
Audio
OUTPUT
Mute
Audio
OUTPUT
Mute
R channel input
XL-UH4H
7 – 11
U6 92L31000240202 : EEPROM ( AM24LC02 ) ( 1/2 )
PIN DESCRIPTION
U6 92L31000240202 : EEPROM ( AM24LC02 ) ( 2/2 )
Figure 7-9 BLOCK DIAGRAM OF IC
A0
1
24LC02
2
3
4
8
7
6
5
A1
A2
VSS
VCC
WP
SCL
SDA
Name
Description
A0, A1, A2
Address Inputs
VSS
Ground
SDA
Data I/O
SCL
Clock Input
WP
White Protect
VCC
Power Input
WP
SDA
SCL
A0
load
inc
ck
start cycle
A1
A2
A2
WORD
ADDRESS
COUNTER
VCC
RW–
Din
VSS
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE
ADDRESS
REGISTER
&
COMPARATOR
DOUT
ACK
YDEC
DATA
REGISTER
Dout
EEPROM
ARRAY
32x8x8
XDEC
H.V.
GENERATION
TIMING
&
CONTROL
XL-UH4H
7 – 12
[2] LCD Display
LCD701 92L22006966425
GRID ASSIGNMENT
OUTER DIMENSIONS
A
1
25
G
D
B
F
C
E
1
25
PATTERN AREA
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