Sharp XL-MP35H (serv.man20) Service Manual ▷ View online
XL-MP35H
– 38 –
44
RVSS
—
—
GND for Right channel. Must be connected to 0 V.
45
RCHO
Output
LVDD /2
Right channel output.
46
RVDD
Input
—
Power supply for Right channel.
47
XVDD
Input
—
Power supply for crystal oscillator.
48
XOUT
Output
Oscillator
Connected for the 33.8688 MHz crystal oscillator ciement.
49
XIN
Input
Oscillator
50
FSX/16MIN
Input/Output
Input
7.35 kHz Synchronization signal monitor port.
or Clock input port for Digital filter & D/A
or Clock input port for Digital filter & D/A
51
XVSS
—
—
Crystal
GND for crystal oscillator. Must be connected to 0 V.
Oscillator
52
C2F
Output
H
C2 FLAG monitor port.
53*
EFLG
Output
L
C1, C2 error corrected monitor port.
54
16MOUT
Output
Clock
16.9344 MHz output port.
55
ASLRCK
Input
—
Left/Right clock input port.
(If this port does not use, must be connect to 0 V.)
(If this port does not use, must be connect to 0 V.)
56
ASDACK
Input
—
Bit clock input port.
(If this port does not use, must be connect to 0 V.)
(If this port does not use, must be connect to 0 V.)
57
ASDFIN
Input
—
Left/Right channel data input port.
(If this port does not use, must be connect to 0 V.)
(If this port does not use, must be connect to 0 V.)
58
LRCK
Output
L
Left/Right clock output port.
59
DATACK
Output
L
Digital data
Bit clock output port.
60
DATA
Output
L
Left/Right channel data output port.
61
CE
Input
—
Chip enable signal input port.
62
CL
Input
—
Microcomputer
Data transfer clock input port.
63
DI
Input
—
Interface
Data input port.
64
DO
Output
(H)
Data output port. (N-ch. open drain output.)
65
*WRQ
Output
H
Interruption signal output.
66
*RES
Input
—
Chip reset signal input port.
This port must be set LOW after first applied power on.
This port must be set LOW after first applied power on.
67
DRF
Output
L
Focus detection output port.
68
VDD5
Input
—
Power supply for Microprocessor.
69
VSS
—
—
GND for digital circuit. Must be connected to 0 V.
70*
CONT3
Input/Output
Input
General purpose port 3.
71*
CONT2
Input/Output
Input
General purpose port 2.
72
CONT1
Input/Output
Input
General purpose port 1.
73
PDO1
Output
—
Internal VCO control phase comparator output port 1.
74
PDO2
Output
Input
Internal VCO control phase comparator output port 2.
75
VVSS
—
—
GND for internal VCO. Must be connected to 0 V.
76
PCKIST
Input
—
PDO output current adjustment resistor connection port.
77
VVDD
Input
—
Power supply for internal VCO.
78
FR
Input
—
VCO frequency range adjustment port.
79
LDS
Input
—
LASER power detected signal input port.
80
LDD
Output
—
LASER power control signal output port.
IC801 VHiLC78646E-1: Servo/Signal Control (LC78646E) (2/2)
Pin No.
Function
Terminal Name Input/Output Setting in Reset
Right channel
D/A converter
D/A converter
Anti-shock
Controlled with serial data command from micro-
computer. When not used, General purpose input/
output terminal. Set it as the input terminal and open
it by connecting to 0 V, or set it as the output terminal
and open it.
computer. When not used, General purpose input/
output terminal. Set it as the input terminal and open
it by connecting to 0 V, or set it as the output terminal
and open it.
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Be sure to supply the same potential to each power terminal. (VVDD, ADAVDD, VDD, LVDD, RVDD, XVDD)
Terminal witch is controlled by the power terminal (VDD5 V) for a microcomputer interface :
CE (61 pin), CL (62 pin), DI (63 pin), DO (64 pin), WRQ (65 pin), RES (66 pin), DRF (67 pin)
Terminal witch is controlled by the power terminal (VDD5 V) for a microcomputer interface :
CE (61 pin), CL (62 pin), DI (63 pin), DO (64 pin), WRQ (65 pin), RES (66 pin), DRF (67 pin)
Crystal
Oscillator
PLL
– 39 –
XL-MP35H
1
2
3
4
5
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7
8
9
10
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12
13
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15
16
17
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20
21
22
23
24
25
26
27
28
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30
31
32
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34
35 36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66 65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SLCO
SLCIST
EFMIN
RF
RFVDD
RFVSS
FIN1
FIN2
TIN1
TIN2
VREF
REF1
FE
TEC
TE
RFMON
JITTC
ADAVDD
ADAVSS
TDO
FDO
SPDO
SLDO
GPDAC
CONT4
CONT5
SBCK/CONT6
SBCK/FG
DEFECT
V/*P
FSEQ
MONI1
MONI2
MONI3
MONI4
MONI5
(3.3V)VSS
VDD
DOUT
TEST
LDD
LDS
FR
VVDD
PCKIST
VVSS
PD02
PD01
CONT1
CONT2
CONT3
VSS
VDD5
DRF
*RES
*WRQ
DO
DI
CL
CE
DATA
DATACK
LRSY
ASDFIN
ASDACK
ASLRCK
16MOUT
EFLG
C2F
XVSS
FSX/16MIN
XIN
XOUT
XVDD
RVDD
RCHO
RVSS
LVSS
LCHO
LVDD
LC78646E
+
–
+
–
–
–
+
+
MIX
LPF
LPF
LPF
TBAL
TBAL
RAM
LEVEL SET
EQ
SW
PH
BH
+
–
+
–
+
–
+
–
MNI
CONT
A/D
SERVO PROCESSOR
TRACK JUMP
AUTO ADJUST
JITTER
DETECT
1bit DAC
8FS
DIGITAL FILTER
GENERAL-PURPOSE
PORTS
COMMAND
INTERFACE
CLOCK
GENERATOR
CLV,CAV
CONTROL
PLL
VCEC
SLICE LEVEL
CONTROL
APC
S/H
D/A
SW
DRF
RUPTURE DEFECT
FRAME SYNC
DETECT,PROTECT INSERT,
EFM DECODE
VDD5V
SUBCODE DECODE CRC
MONITOR SIGNAL SELECTOR
RAM
ERROR
CORRECTION
AUDIO CD
C1-2,C2-2
AUDIO OUT
SERIAL
OUT
EXTERNAL
AUDIO IN
INTERPOLATION
MUTE
ATTENUATION
DEEMPHSIS
LPF
FIN1
FIN2
TIN1
TIN2
REF1
DEFECT
ADIN
ADAVDD
ADAVSS
JITTC
SLCO
EFMIN
SLCIST
PCK
PDO1
PDO2
PDO2
FR
PCKIST
VVDD
VVSS
SBCK/FG
XIN
XOUT
16MOUT
XVDD
XVSS
*RES
*WRQ
CL
CE
DI
DO
VDD5V
CONT1, 2, 3
TEST
CONT4, 5,
SBCK/CONT6
LVDD
LVSS
LCHO
RCHO
RVDD
RVSS
ASDFIN
ASDACK
ASLRCK
DATA
DATACK
LRSY
DOUT
EFLG
C2F
FSX/16MIN
MONI1~5
VSS
VDD
V/*P
FSEQ
DRF
GPDAC
SPD0
SLD0
TD0
FD0
LDS
LDD
VREF
RFMON
RFVSS
RFVDD
RF
TEC
TE
FE
+
–
+
–
AGC
IC801 VHiLC78646E-1: Servo/Signal Control (LC78646E)
Figure 39 BLOCK DIAGRAM OF IC
– 39 –
XL-MP35H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35 36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66 65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SLCO
SLCIST
EFMIN
RF
RFVDD
RFVSS
FIN1
FIN2
TIN1
TIN2
VREF
REF1
FE
TEC
TE
RFMON
JITTC
ADAVDD
ADAVSS
TDO
FDO
SPDO
SLDO
GPDAC
CONT4
CONT5
SBCK/CONT6
SBCK/FG
DEFECT
V/*P
FSEQ
MONI1
MONI2
MONI3
MONI4
MONI5
(3.3V)VSS
VDD
DOUT
TEST
LDD
LDS
FR
VVDD
PCKIST
VVSS
PD02
PD01
CONT1
CONT2
CONT3
VSS
VDD5
DRF
*RES
*WRQ
DO
DI
CL
CE
DATA
DATACK
LRSY
ASDFIN
ASDACK
ASLRCK
16MOUT
EFLG
C2F
XVSS
FSX/16MIN
XIN
XOUT
XVDD
RVDD
RCHO
RVSS
LVSS
LCHO
LVDD
LC78646E
+
–
+
–
–
–
+
+
MIX
LPF
LPF
LPF
TBAL
TBAL
RAM
LEVEL SET
EQ
SW
PH
BH
+
–
+
–
+
–
+
–
MNI
CONT
A/D
SERVO PROCESSOR
TRACK JUMP
AUTO ADJUST
JITTER
DETECT
1bit DAC
8FS
DIGITAL FILTER
GENERAL-PURPOSE
PORTS
COMMAND
INTERFACE
CLOCK
GENERATOR
CLV,CAV
CONTROL
PLL
VCEC
SLICE LEVEL
CONTROL
APC
S/H
D/A
SW
DRF
RUPTURE DEFECT
FRAME SYNC
DETECT,PROTECT INSERT,
EFM DECODE
VDD5V
SUBCODE DECODE CRC
MONITOR SIGNAL SELECTOR
RAM
ERROR
CORRECTION
AUDIO CD
C1-2,C2-2
AUDIO OUT
SERIAL
OUT
EXTERNAL
AUDIO IN
INTERPOLATION
MUTE
ATTENUATION
DEEMPHSIS
LPF
FIN1
FIN2
TIN1
TIN2
REF1
DEFECT
ADIN
ADAVDD
ADAVSS
JITTC
SLCO
EFMIN
SLCIST
PCK
PDO1
PDO2
PDO2
FR
PCKIST
VVDD
VVSS
SBCK/FG
XIN
XOUT
16MOUT
XVDD
XVSS
*RES
*WRQ
CL
CE
DI
DO
VDD5V
CONT1, 2, 3
TEST
CONT4, 5,
SBCK/CONT6
LVDD
LVSS
LCHO
RCHO
RVDD
RVSS
ASDFIN
ASDACK
ASLRCK
DATA
DATACK
LRSY
DOUT
EFLG
C2F
FSX/16MIN
MONI1~5
VSS
VDD
V/*P
FSEQ
DRF
GPDAC
SPD0
SLD0
TD0
FD0
LDS
LDD
VREF
RFMON
RFVSS
RFVDD
RF
TEC
TE
FE
+
–
+
–
AGC
IC801 VHiLC78646E-1: Servo/Signal Control (LC78646E)
Figure 39 BLOCK DIAGRAM OF IC
– 39 –
XL-MP35H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35 36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66 65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SLCO
SLCIST
EFMIN
RF
RFVDD
RFVSS
FIN1
FIN2
TIN1
TIN2
VREF
REF1
FE
TEC
TE
RFMON
JITTC
ADAVDD
ADAVSS
TDO
FDO
SPDO
SLDO
GPDAC
CONT4
CONT5
SBCK/CONT6
SBCK/FG
DEFECT
V/*P
FSEQ
MONI1
MONI2
MONI3
MONI4
MONI5
(3.3V)VSS
VDD
DOUT
TEST
LDD
LDS
FR
VVDD
PCKIST
VVSS
PD02
PD01
CONT1
CONT2
CONT3
VSS
VDD5
DRF
*RES
*WRQ
DO
DI
CL
CE
DATA
DATACK
LRSY
ASDFIN
ASDACK
ASLRCK
16MOUT
EFLG
C2F
XVSS
FSX/16MIN
XIN
XOUT
XVDD
RVDD
RCHO
RVSS
LVSS
LCHO
LVDD
LC78646E
+
–
+
–
–
–
+
+
MIX
LPF
LPF
LPF
TBAL
TBAL
RAM
LEVEL SET
EQ
SW
PH
BH
+
–
+
–
+
–
+
–
MNI
CONT
A/D
SERVO PROCESSOR
TRACK JUMP
AUTO ADJUST
JITTER
DETECT
1bit DAC
8FS
DIGITAL FILTER
GENERAL-PURPOSE
PORTS
COMMAND
INTERFACE
CLOCK
GENERATOR
CLV,CAV
CONTROL
PLL
VCEC
SLICE LEVEL
CONTROL
APC
S/H
D/A
SW
DRF
RUPTURE DEFECT
FRAME SYNC
DETECT,PROTECT INSERT,
EFM DECODE
VDD5V
SUBCODE DECODE CRC
MONITOR SIGNAL SELECTOR
RAM
ERROR
CORRECTION
AUDIO CD
C1-2,C2-2
AUDIO OUT
SERIAL
OUT
EXTERNAL
AUDIO IN
INTERPOLATION
MUTE
ATTENUATION
DEEMPHSIS
LPF
FIN1
FIN2
TIN1
TIN2
REF1
DEFECT
ADIN
ADAVDD
ADAVSS
JITTC
SLCO
EFMIN
SLCIST
PCK
PDO1
PDO2
PDO2
FR
PCKIST
VVDD
VVSS
SBCK/FG
XIN
XOUT
16MOUT
XVDD
XVSS
*RES
*WRQ
CL
CE
DI
DO
VDD5V
CONT1, 2, 3
TEST
CONT4, 5,
SBCK/CONT6
LVDD
LVSS
LCHO
RCHO
RVDD
RVSS
ASDFIN
ASDACK
ASLRCK
DATA
DATACK
LRSY
DOUT
EFLG
C2F
FSX/16MIN
MONI1~5
VSS
VDD
V/*P
FSEQ
DRF
GPDAC
SPD0
SLD0
TD0
FD0
LDS
LDD
VREF
RFMON
RFVSS
RFVDD
RF
TEC
TE
FE
+
–
+
–
AGC
IC801 VHiLC78646E-1: Servo/Signal Control (LC78646E)
Figure 39 BLOCK DIAGRAM OF IC
Display