Sharp XL-MP100H (serv.man13) Service Manual ▷ View online
XL-MP100H
8 – 7
IC801 VHIMN6627933C: CD Digital Signal Processor (MN6627933C) (2/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
NOTE: Signals with * are switched to other signals by microcomputer command.
DRAM pins differ in specifications depending on the type and capacity.
NOTE: When sharing the PCB with MN6627932, connect pins as follows:
No. 62 pin (N.C. pin) = L (fixed), No. 54 pin (N.C. pin): LOVDD2, No. 65 pin (N.C. pin): LOVSS2
Refer to the MN6627932 specifications for the product details.
Pin No.
Terminal Name
I/O
Function
58
LOOUTL
O
Left channel audio signal output for line-out output
59
LOVSS1
I
Line-out output GND
60
LOOUTR
O
Right channel audio signal output for line-out output
61
LOVDD1
I
Line-out output power supply
62*
N.C.
—
63*
TMON
O
Test monitor output 1
64
N.C.
—
65
N.C.
—
66*
TMON2
O
Test monitor output 2
67
DVDD3
I
Digital circuit power supply 3
68
DVSS2
I
Digital circuit GND 2
69*
*EXT0
I/O
Extended input/output port 0
70*
*EXT1
I/O
Extended input/output port 1
71*
*EXT2
I/O
Extended input/output port 2
72
MCLK
I
Microcomputer command clock signal input
73
MDATA
I
Microcomputer command data signal input
74
MLD
I
Microcomputer command load signal input
75
*STAT
O
Status signal output
76
*BLKCK
O
Sub code block clock signal output
77*
*SMCK
O
4.2336/8.4672 MHz clock signal output
78*
*PMCK
O
88.2 kHz clock signal output
79
*TX
O
Digital audio interface signal output
80
*FLAG
O
Flag signal output
81
NRST
I
LSI reset signal input
82
NTEST
I
Test mode setting input
83
DVSS3
I
Digital circuit GND 3
84
X1
I
Crystal oscillation circuit input
85
X2
O
Crystal oscillation circuit output
86
IOVDD2
I
Digital I/O power supply 2
87
DVDD2
I
Internal digital circuit power supply 2
88
D2
I/O
DRAM data signal input/output 2
89
D1
I/O
DRAM data signal input/output 1
90
D0
I/O
DRAM data signal input/output 0
91
D3
I/O
DRAM data signal input/output 3
92
D4
I/O
DRAM data signal input/output 4
93
D5
I/O
DRAM data signal input/output 5
94
D6
I/O
DRAM data signal input/output 6
95
D7
I/O
DRAM data signal input/output 7
96
D15
I/O
DRAM data signal input/output 15
97
D14
I/O
DRAM data signal input/output 14
98
DRVDD2
I
DRAM interface I/O power supply 2
99
D13
I/O
DRAM data signal input/output 13
100
D12
I/O
DRAM data signal input/output 12
XL-MP100H
8 – 8
IC801 VHIMN6627933C: CD Digital Signal Processor (MN6627933C)
STAT
*
MLD
MDATA
MCLK
EXT2
*
EXT1
*
EXT0
*
DV
S
S
2
DV
DD3
TM
O
N
2
NC
NC
TM
O
N
1
NC
LO
V
DD1
LOOUTR
LO
V
S
S1
LOOUT
L
AVS
S
PL
LF
O
PL
LF
PWMS
EL
DS
LF
AR
F
IREF
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
BLKCK *
76
50 AVDD
SMCK *
77
49 BDO
PMCK *
78
48 OFT
TX *
79
47 NRFDET
FLAG *
80
46 LDON
NRST
81
45 RFENV
NTEST
82
44 ADPVCC
DVSS3
83
43 TE
X1
84
42 FE
X2
85
41 FBAL
IOVDD2
86
40 TBAL
DVDD2
87
39 IOVDD1
D2
88
38 FOM *
D1
89
37 FOP
D0
90
36 TRM *
D3
91
35 TRP
D4
92
34 TRVM2 *
D5
93
33 TRVP2 *
D6
94
32 TRVM *
D7
95
31 TRVP
D15
96
30 SPPOL *
D14
97
29 SPOUT
DRVDD2
98
28 DVDD1
D13
99
27 BA0 *
D12 100
26 BA1 *
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
D11
D10
D9
D8
UD
QM
SD
R
C
K
A11
A9
A8
A7
A6
A5
A4
LD
Q
M
NW
E
NC
A
S
NR
A
S
NC
S
A3
A2
A1
A0
DRV
D
D
DV
S
S
1
A1
0
M N 6 6 2 7 9 3 3 C
NTEST
NRST
ADPVCC
FE
TE
RFENV
OF
NRFDET
BDO
SPPO
PWMSE
SPOU
TRV
TRV
* TRVM
* TRV
TR
TR
TBA
FO
FO
FBA
LDO
*
*
*
*
* T
EX
EX
EX
*
*
*
TMO
TMO
T
L
L
T
P
M
2
P2
M
P
L
M
P
L
N
X
T0
T1
T2
N1
N2
TL
TR
LO
V
D
D
1
LO
V
S
S
1
K
IN
(E
X
T
K
IN
(E
X
T
S
R
D
A
TIN
(E
X
T
LO
O
U
LO
O
U
D
V
S
S
2
D
V
S
S
3
D
V
S
S
1
IO
V
D
D
1
IO
V
D
D
2
LR
C
1)
B
C
L
2)
0)
CIRC
EFM DEMODULATION
SYNC INTERPOLATION
CIRC ECC
CDROM ECC
CIRC ECC
CDROM ECC
BUS CONTROL UNIT
(BCU)
ADPCM
SERIAL OUTPUT
INTERFACE
MP3
DECORDER
FS
CONVERTER
SPINDLE
SERVO
SERVO
CPU
CONVERTER
INPUT PORT
A/D
OUTPUT
PORT
DIGITAL OUT
DIGITAL FILTER
DAC
PWM LOGIC
ANALOG
LOWPASS
FILTER
REGULATER
DVDD
1bit
SUBCODE
INTERFACE
DRAM
INTERFACE
RAM
X
1
X
2
S
M
C
K
P
M
C
K
*
S
TA
T
M
LD
M
C
LK
M
D
A
TA
* *
TIMING
GENERATOR
MICRO COMPUTER
INTERFACE
DS PLL VCO
A
R
F
IR
E
F
D
S
LF
P
LL
F
P
LL
FO
A
V
S
S
A
V
D
D
L
TXTCK
(EXT1)
TXTD
(EXT0)
DQSY_TXT
(EXT2)
SBCK
(EXT1)
SUBC
(EXT0)
TXNCLDCK
(EXT2)
FLAG
*
BLKCK
*
A11~A0
D15~D0
NCAS
NRAS
NWE
NCS
NCAS
NRAS
NWE
NCS
SDRCK
* BA0
* BA1
* BA1
UDQM
LDQM
DRVDD1
DRVDD2
LDQM
DRVDD1
DRVDD2
LRCK(EXT1)
BCLK(EXT2)
SRDATA
(EXT0)
Figure 7 BLOCK DIAGRAM OF IC
XL-MP100H
8 – 9
IC802 RH-iXA018SJZZ: MP3 DECODER (IXA018SJ)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SBO2/P03 SBI2/P04 SBT2/P05
NDK/BUZZER/P06
NRST/P27
RMOUT/TCIO0/P10
TCIO1/P11 TCIO2/P12 TCIO3/P13 TCIO7/P14 IRQ0/P20
ACZ/IRQ1/P21
IRQ2/P22 IRQ3/P23 IRQ4/P24 SBO3/P30
SYSCLK/SBI3/P31
SBT3/P32
P33 P34
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P50/NWE
P47/KEY7/A15
P46/KEY6/A14
P45/KEY5/A9
P44/KEY4/A8
P43/TCIO5/KEY3
P42/SBT0/KEY2
P41/RXD0/SBI0/KEY1
P40/TXD0/SBO0/KEY0
P37/TCIO4
P36/SDA4
P35/SCL4
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P80/LED0,D0 P81/LED1,D1 P82/LED2,D2 P83/LED3,D3 P84/LED4,D4 P85/LED5,D5 P86/LED6,D6 P87/LED7,D7 P77/SDO7 P76/SDO6 P75/A13/SDO5 P74/A12/SDO4 P73/A11/SDO3 P72/A10/SDO2 P71/SDO1 P70/SDO0 P67/A7 P66/A6 P65/A5 P64/A4
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
VREF-
AN0/PA0
AN1/PA1
AN2/PA2
AN3/PA3
AN4/PA4
AN5/PA5
AN6/PA6
NC(VPP)
VREF+
VDD
OSC2
OSC1
VSS
XI
XO
MMOD
TXD1/SBO1/P00
SDA4/RXD1/SBI1/P01
SCL4/SBT1/P02
P63/A3
P62/A2
P61/A1
P60/A0
P54/A17
P53/A16
P52/IRQ5/NCS
P51/NRE
OSC1
OSC2
XI
XO
VSS VDD
MMOD
SDA4,RXD1,SBI1,P01
SCL4,SBT1,P02
SBO2,P03
SBI2,P04
SBT2,P05
NDK,BUZZER,P06
TXD1,SBO1,P00
TCIO1,P11
TCIO2,P12
TCIO3,P13
TCIO7,P14
TCIO2,P12
TCIO3,P13
TCIO7,P14
RMOUT,TCIO0,P10
ACZ,IRQ1,P21
IRQ2,P22
IRQ3,P23
IRQ4,P24
IRQ0,P20
SYSCLK,SBI3,P31
SBT3,P32
P33
P34
SCL4,P35
SDA4,P36
TCIO4,P37
SBO3,P30
NRST,P27
TXD0,SBO0,KEY0,P40 RXD0,SBI0,KEY1,P41
SBT0,KEY2,P42 TCIO5,KEY3,P43
A8,KEY4,P44 A9,KEY5,P45 A14,KEY6,P46 A15,KEY7,P47
NWE,P50
NRE,P51
IRQ5,NCS,P52
A16,P53
A17,P54
A0,P60 A1,P61 A2,P62 A3,P63 A4,P64 A5,P65 A6,P66 A7,P67
VREF-
VREF+
P76,SDO6
P75,A13,SDO5
P74,A12,SDO4
P73,A11,SDO3
P72,A10,SDO2
P71,SDO1
P70,SDO0
P77,SDO7
P86,D6,LED6
P85,D5,LED5
P84,D4,LED4
P83,D3,LED3
P82,D2,LED2
P81,D1,LED1
P80,D0,LED0
P87,D7,LED7
PA5,AN5
PA4,AN4
PA3,AN3
PA2,AN2
PA1,AN1
PA0,AN0
PA6,AN6
PORT
0
PORT
7
P
ORT
8
PORT
A
PORT
3
P
ORT
2
PORT
1
CPU
MN101C
SUB CLOCK
OSCILLATOR
8bit TIMER0
8bit TIMER1
8bit TIMER2
8bit TIMER1
8bit TIMER2
8bit TIMER3
8bit TIMER4
8bit TIMER4
TIME BASE TIMER6
SERIAL INTERFACE1
SERIAL INTERFACE2
SERIAL INTERFACE2
SERIAL INTERFACE3
WATCH DOG TIMER
DATA AUTO
TRANSMISSION
A/D CONVERTER
OUTSIDE INTERRUPT
16bit TIMER7
PORT 4
PORT 6
PORT 5
SERIAL INTERFACE0
8bit TIMER5
SERIAL INTERFACE4
SYSTEM CLOCK
OSCILLATOR
ROM
64Kbyte
RAM
2Kbyte
Figure 8 BLOCK DIAGRAM OF IC
XL-MP100H
8 – 10
IC803 VHIAN22004A-1: Servo Amp. (AN22004A)
5
6
7
13
12
14
9
10
15
22
23
20
21
2
1
3
17
16
25
26
24
19
27
28
29
30
31
32
18
4
EQSW
EQBST
A
C
B
D
F
E
VREF
GCTL
TBAL
FBAL
LDON
GND
VCC
PD
LD
TE
TEN
FE
FEN
NRFDET
3TOUT
CEA
BDO
BDO
DCDET
ARF
CA
GC
RFIN
RFOUT
BDO/OFTR
3TENV
NRFDET
AGC
RFEQ
BandGap
RFAMP
SUB
SUB
AMP
GCA
BCA
AMP
GCA
BCA
AMP
GCA
BCA
AMP
GCA
BCA
11
8
Figure 9 BLOCK DIAGRAM OF IC
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