Sharp XL-HP700 (serv.man17) Service Manual ▷ View online
– 41 –
XL-HP700H
44
RVSS
—
—
GND for Right channel. Must be connected to 0 V.
45
RCHO
Output
LVDD /2
Right channel output.
46
RVDD
Input
—
Power supply for Right channel.
47
XVDD
Input
—
Power supply for crystal oscillator.
48
XOUT
Output
Oscillator
Connected for the 33.8688 MHz crystal oscillator ciement.
49
XIN
Input
Oscillator
50
FSX/16MIN
Input/Output
Input
7.35 kHz Synchronization signal monitor port.
or Clock input port for Digital filter & D/A
or Clock input port for Digital filter & D/A
51
XVSS
—
—
Crystal
GND for crystal oscillator. Must be connected to 0 V.
Oscillator
52*
C2F
Output
H
C2 FLAG monitor port.
53*
EFLG
Output
L
C1, C2 error corrected monitor port.
54*
16MOUT
Output
Clock
16.9344 MHz output port.
55
ASLRCK
Input
—
Left/Right clock input port.
(If this port does not use, must be connect to 0 V.)
(If this port does not use, must be connect to 0 V.)
56
ASDACK
Input
—
Bit clock input port.
(If this port does not use, must be connect to 0 V.)
(If this port does not use, must be connect to 0 V.)
57
ASDFIN
Input
—
Left/Right channel data input port.
(If this port does not use, must be connect to 0 V.)
(If this port does not use, must be connect to 0 V.)
58*
LRCK
Output
L
Left/Right clock output port.
59*
BCK
Output
L
Digital data
Bit clock output port.
60*
DATA
Output
L
Left/Right channel data output port.
61
CE
Input
—
Chip enable signal input port.
62
CL
Input
—
Microcomputer
Data transfer clock input port.
63
DI
Input
—
Interface
Data input port.
64
DO
Output
(H)
Data output port. (N-ch. open drain output.)
65
*WRQ
Output
H
Interruption signal output.
66
*RES
Input
—
Chip reset signal input port.
This port must be set LOW after first applied power on.
This port must be set LOW after first applied power on.
67
DRF
Output
L
Focus detection output port.
68
VDD5
Input
—
Power supply for Microprocessor.
69
VSS
—
—
GND for digital circuit. Must be connected to 0 V.
70*
CONT3
Input/Output
Input
General purpose port 3.
71*
CONT2
Input/Output
Input
General purpose port 2.
72*
CONT1
Input/Output
Input
General purpose port 1.
73
PDO1
Output
—
Internal VCO control phase comparator output port 1.
74
PDO2
Output
Input
Internal VCO control phase comparator output port 2.
75
VVSS
—
—
GND for internal VCO. Must be connected to 0 V.
76
PCKIST
Input
—
PDO output current adjustment resistor connection port.
77
VVDD
Input
—
Power supply for internal VCO.
78
FR
Input
—
VCO frequency range adjustment port.
79
LDS
Input
—
LASER power detected signal input port.
80
LDD
Output
—
LASER power control signal output port.
IC1 VHiLC78646E-1: CD Servo (LC78646E) (2/2)
Pin No.
Function
Terminal Name Input/Output Setting in Reset
Right channel
D/A converter
D/A converter
Anti-shock
Controlled with serial data command from micro-
computer. When not used, General purpose input/
output terminal. Set it as the input terminal and open
it by connecting to 0 V, or set it as the output terminal
and open it.
computer. When not used, General purpose input/
output terminal. Set it as the input terminal and open
it by connecting to 0 V, or set it as the output terminal
and open it.
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Be sure to supply the same potential to each power terminal. (VVDD, ADAVDD, VDD, LVDD, RVDD, XVDD)
Terminal witch is controlled by the power terminal (VDD5 V) for a microcomputer interface :
CE (61 pin), CL (62 pin), DI (63 pin), DO (64 pin), WRQ (65 pin), RES (66 pin), DRF (67 pin)
Terminal witch is controlled by the power terminal (VDD5 V) for a microcomputer interface :
CE (61 pin), CL (62 pin), DI (63 pin), DO (64 pin), WRQ (65 pin), RES (66 pin), DRF (67 pin)
Crystal
Oscillator
PLL
XL-HP700H
– 42 –
Figure 42 BLOCK DIAGRAM OF IC
IC1 VHiLC78646E-1: CD Servo (LC78646E)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35 36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66 65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SLCO
SLCIST
EFMIN
RF
RFVDD
RFVSS
FIN1
FIN2
TIN1
TIN2
VREF
REF1
FE
TEC
TE
RFMON
JITTC
ADAVDD
ADAVSS
TDO
FDO
SPDO
SLDO
GPDAC
CONT4
CONT5
SBCK/CONT6
SBCK/FG
DEFECT
V/*P
FSEQ
MONI1
MONI2
MONI3
MONI4
MONI5
(3.3V)VSS
VDD
DOUT
TEST
LDD
LDS
FR
VVDD
PCKIST
VVSS
PD02
PD01
CONT1
CONT2
CONT3
VSS
VDD5
DRF
*RES
*WRQ
DO
DI
CL
CE
DATA
DATACK
LRSY
ASDFIN
ASDACK
ASLRCK
16MOUT
EFLG
C2F
XVSS
FSX/16MIN
XIN
XOUT
XVDD
RVDD
RCHO
RVSS
LVSS
LCHO
LVDD
LC78646E
+
–
+
–
–
–
+
+
MIX
LPF
LPF
LPF
TBAL
TBAL
RAM
LEVEL SET
EQ
SW
PH
BH
+
–
+
–
+
–
+
–
MNI
CONT
A/D
SERVO PROCESSOR
TRACK JUMP
AUTO ADJUST
JITTER
DETECT
1bit DAC
8FS
DIGITAL FILTER
GENERAL-PURPOSE
PORTS
COMMAND
INTERFACE
CLOCK
GENERATOR
CLV,CAV
CONTROL
PLL
VCEC
SLICE LEVEL
CONTROL
APC
S/H
D/A
SW
DRF
RUPTURE DEFECT
FRAME SYNC
DETECT,PROTECT INSERT,
EFM DECODE
VDD5V
SUBCODE DECODE CRC
MONITOR SIGNAL SELECTOR
RAM
ERROR
CORRECTION
AUDIO CD
C1-2,C2-2
AUDIO OUT
SERIAL
OUT
EXTERNAL
AUDIO IN
INTERPOLATION
MUTE
ATTENUATION
DEEMPHSIS
LPF
FIN1
FIN2
TIN1
TIN2
REF1
DEFECT
ADIN
ADAVDD
ADAVSS
JITTC
SLCO
EFMIN
SLCIST
PCK
PDO1
PDO2
PDO2
FR
PCKIST
VVDD
VVSS
SBCK/FG
XIN
XOUT
16MOUT
XVDD
XVSS
*RES
*WRQ
CL
CE
DI
DO
VDD5V
CONT1, 2, 3
TEST
CONT4, 5,
SBCK/CONT6
LVDD
LVSS
LCHO
RCHO
RVDD
RVSS
ASDFIN
ASDACK
ASLRCK
DATA
DATACK
LRSY
DOUT
EFLG
C2F
FSX/16MIN
MONI1~5
VSS
VDD
V/*P
FSEQ
DRF
GPDAC
SPD0
SLD0
TD0
FD0
LDS
LDD
VREF
RFMON
RFVSS
RFVDD
RF
TEC
TE
FE
+
–
+
–
AGC
– 43 –
XL-HP700H
IC2 VHIM63001FP-1: Focus/Tracking/Spin/Sled Driver (MP63001FP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
IN2–
IN1A–
IN1B–
OUT1–
OUT1+
OUT2–
OUT2+
OUT3+
OUT3–
IN3–
VCC1
STANDBY
VREF
MUTE
IN6+
IN6–
VCC4
OUT6–
OUT6+
OUT5–
OUT5+
VCC3
OUT4+
OUT4–
IN4–
VCC2
IN5+
IN5–
MP63001FP
GND
GND
10K
IN1B–
IN1A–
13.3K
10K
13.3K
VCC1
5K
OUT1+
IoMAX
300mA
FOCUS
OUT1–
5K
10K
10K
+
–
VCC1
+
–
10K
IN2–
13.3K
10K
13.3K
VCC1
5K
OUT2+
IoMAX
300mA
TRACKING
OUT2–
VREFM1
5K
+
–
VCC1
+
–
VCC1
LOW.OPEN:DISABLE
10K
IN5–
STANDBY
CH1~6
IN5+
12.5K
10K
12.5K
VCC3
5K
OUT5+
VREFMAMP
VCC3
VCC3
IoMAX
300mA
LOADING
OUT5–
5K
+
–
+
–
VCC3
+
–
10K
IN3–
VREF
13.3K
10K
13.3K
VCC1
VCC1
5K
OUT3+
IoMAX
300mA
SLIDE
OUT3–
GND GND
5K
+
–
VCC1
+
–
10K
IN4–
VREF
TSD
13.3K
10K
13.3K
VCC2
5K
OUT4+
IoMAX
500mA
SPM
OUT4–
5K
+
–
VCC2
+
–
10K
IN6–
VCC4
IN6+
12.5K
10K
12.5K
VCC4
5K
OUT6+
VREFMAMP
VREFM4
VREFM3
VCC4
IoMAX
300mA
CHANGER
OUT6–
5K
+
–
+
–
VCC4
+
–
VCC1
VREFMAMP
VCC1
+
–
STANDBY
10K
10K
VCC1
H:DISABLE
MUTE
CH6
MUTE
VCC2
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Terminal Name
Pin No.
Function
1
IN2–
CH2 inverted input
2
IN1A–
CH1 inverted input
3
IN1B–
CH1 output offset control
4
OUT1–
CH1 inverted output
5
OUT1+
CH1 non-inverted output
6
OUT2–
CH2 inverted output
7
OUT2+
CH2 non-inverted output
8-14
GND
GND
15
OUT3+
CH3 non-inverted output
16
OUT3–
CH3 inverted output
17
IN3–
CH3 inverted input
18
VCC1
Power supply 1 (CH1,CH2,CH3)
19
STANDBY
STANDBY signal input
20
VREF
CH1-CH4 Reference voltage input
21
MUTE
MUTE SIGNAL INPUT (CH6)
Terminal Name
Pin No.
Function
22
IN5–
CH5 inverted input
23
IN5+
CH5 non-inverted output
24
VCC2
Power supply 2 (CH4)
25
IN4–
CH4 inverted input
26
OUT4–
CH4 inverted output
27
OUT4+
CH4 non-inverted output
28
VCC3
Power supply 3 (CH5)
29-35
GND
GND
36
OUT5+
CH5 non-inverted output
37
OUT5–
CH5 inverted output
38
OUT6+
CH6 non-inverted output
39
OUT6–
CH6 inverted output
40
VCC4
Power supply 4 (CH6)
41
IN6–
CH6 inverted input
42
IN6+
CH6 non-inverted input
Figure 43 BLOCK DIAGRAM OF IC
XL-HP700H
– 44 –
IC601 VHiLC75341/-1: Audio Processor (LC75341)
Figure 44 BLOCK DIAGRAM OF IC
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
17
LVref
RVref
CONTROL
CIRCUIT
CONTROL
CIRCUIT
CONTROL
CIRCUIT
LOUT
LBASS
LIN
LSEL0
L4
L3
L2
L1
R1
R2
R3
R4
RSEL0
RIN
RTRE
LTRE
RBASS
ROUT
VREF
VDD
CLK
DI
CE
VSS
CCB
INTERFACE
CD
Tuner
Tape
Video
IC601 VHiLC75341/-1: Audio Processor (LC75341)
Terminal Name
Pin No.
Function
1
DI
Serial data and clock input pin
for control.
for control.
2
CE
Chip enable pin.
Data written into an internal latch
in a timing of "H" to "L".
Each analog switch is activated.
Data transfer enabled at "H" level.
Data written into an internal latch
in a timing of "H" to "L".
Each analog switch is activated.
Data transfer enabled at "H" level.
3
VSS
Ground pin.
4
LOUT
Bass band filter comprising
capacitor and resistor connection
pin and bass/treble output pin.
capacitor and resistor connection
pin and bass/treble output pin.
5
LBASS
Bass band filter comprisingcapacitor
and resistor connection pin.
and resistor connection pin.
6
LTRE
Treble band filter comprising
capacitor and resistor connection
pin.
capacitor and resistor connection
pin.
7
LIN
Volume + equaliser output pin
8
LSEL0
Input selector output pin.
9-12
L4-1
Input signal pin.
Terminal Name
Pin No.
Function
13-16
R1-4
Input signal pin.
17
RSEL0
Input selector output pin.
18
RIN
Volume + equaliser output pin
19
RTRE
Treble band filter comprising
capacitor and resistor connection
pin.
capacitor and resistor connection
pin.
20
RBASS
Bass band filter comprisingcapacitor
and resistor connection pin.
and resistor connection pin.
21
ROUT
Bass band filter comprising
capacitor and resistor connection
pin and bass/treble output pin.
capacitor and resistor connection
pin and bass/treble output pin.
22
VREF
0.5x VDD voltage generation block
for analog ground. Capacitor of
several 10
for analog ground. Capacitor of
several 10
µ
F to be connected
between VREF and AWSS (VSS) as
a countermeasure against power
ripple.
a countermeasure against power
ripple.
23
VDD
Supply pin
24
CLK
Serial data and clock input pin
for control.
for control.
Display
