Sharp XL-HP535 (serv.man3) Service Manual ▷ View online
XL-HP535H/HP535E
8 – 5
IC2 VHILA6261//-1: Focus/Tracking/Spin/Sled Driver (LA6261)
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11k
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22k
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Pre
D
rive
Pre
D
rive
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Refcronce
voltage
DUFFER AMP
For 1/2 VCC
DUFFER AMP
For VREF
TSD
Bandgad
BTL
Mode
select
Mode
select
CH4
CH5
CH6
CH3
CH2
CH1
VOLTAGE
CONTROL AMP
Figure 2 BLOCK DIAGRAM OF IC
XL-HP535H/HP535E
8 – 6
IC3 VHiLC78683E-1: MP3 Decoder (LC78683E) (1/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No.
Terminal Name
Input/Output
Block
Function
1
LRSY
Input
CD IF
CD left/right clock input.
2
ADDATA
Output
Audio interface
Audio data output.
3
ADBCK
Output
Audio bit clock output.
4
ADLRCK
Output
Audio left/right clock output.
5
C2FIN
Input
CD IF
CD C2 error flag input.
6
TEST1
Input
Test
Test input 1. (This pin must be connected to ground during normal opera-
tion.)
tion.)
7
CKIN
Input
CLOCK
System clock input.(16.9344 MHz)
8
VSS
—
Power supply
Ground
9
CKOUT
Output
CLOCK
Extemal digital filter and D/A converter clock (384 fs) output.
10
TEST2
Input
Test
Test input 2.(This pin must be connected to ground during normal operation.)
11
DVDD1
—
Power supply
Digital I/O system power supply.
12
PW
Input
Subcode interface
CD subcode data serial input
13
SBSY
Input
CD subcode block sync signal input.
14
SFSY
Input
CD subcode frame sync signal input
15*
SBCK
Output
CD subcode transfer serial clock output.
16
AVDD
—
Power supply
Analog system (PLL) power supply.
17
VPRFR
—
PLL
VCO oscillator range setting
18
VCOC
Input
VCO control voltage input.
19
VPDO
Output
VCO charge pump output.
20
AVSS
—
Power supply
Analog system ground
21
DVDD2
—
Internal logic system power supply.
22
VSS
—
GND
23
MDATA0
Input/Output
Memory interface
DRAM data bus 0
24
MDATA1
Input/Output
DRAM data bus 1
25
MDATA2
Input/Output
DRAM data bus 2
26
MDATA3
Input/Output
DRAM data bus 3
27
MDATA4
Input/Output
DRAM data bus 4
28
MDATA5
Input/Output
DRAM data bus 5
29
MDATA6
Input/Output
DRAM data bus 6
30
MDATA7
Input/Output
DRAM data bus 7
31
DVDD3
—
Power supply
Digital I/O system power supply
32
VSS
—
GND
33
MDATA8
Input/Output
Memory interface
DRAM data bus 8
34
MDATA9
Input/Output
DRAM data bus 9
35
MDATA10
Input/Output
DRAM data bus 10
36
MDATA11
Input/Output
DRAM data bus 11
37
MDATA12
Input/Output
DRAM data bus 12
38
MDATA13
Input/Output
DRAM data bus 13
39
MDATA14
Input/Output
DRAM data bus 14
40
MDATA15
Input/Output
DRAM data bus 15
41
RASB
Output
RAS output (active low)
42
WEB
Output
WE output (active low)
43
CASLB
Output
CAS output (lower byte, active)
44
CASLB
Output
CAS output (upper byte, active)
45
OEB
Output
OE output (active low)
46*
MADRS12
Output
DRAM address output12
47*
MADRS11
Output
DRAM address output11
48*
MADRS10
Output
DRAM address output10
49*
MADRS9
Output
DRAM address output 9
50
MADRS8
Output
DRAM address output 8
XL-HP535H/HP535E
8 – 7
IC3 VHiLC78683E-1: MP3 Decoder (LC78683E) (2/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
NOTE: 1) Notes on unused pins
Unused input pins must be connected to the ground level (0V).
Unused output pins must be left open. Do not connect anything to these pins.
Unused I/O pins may either be connected to the ground level (0V) or set to output mode and left open.
2) The corresponding power supply levels must be provided to all of the DVDD1, DVDD3, DVDD4, DVDD6, and AVDD pins. The correspond-
ing power supply level must also be provided to DVDD2 and DVDD5. (See the Allowable Operating Ranges specifications for the supply
levels.)
levels.)
3) The TEST1 and TEST2 input pins must be connected to ground (0V).
4) The I/O pins (MDA0:15, STREQ, STCK, and STDAT) go to input mode after a reset.
5) After fist applying the power supply levels, the RESB pin must be held low for at least 1
µs.
6) A 16.9344 MHz clock signal must be supplied to the CKIN pin by the CD DSP.
The LC786484E does not support the implementation of an oscillator circuit using an oscillator element.
Pin No.
Terminal Name
Input/Output
Block
Function
51
DVDD4
—
Power supply
Digital I/O system power supply.
52
VSS
—
GND
53
MADRS7
Output
Memory interface
DRAM address output 7.
54
MADRS6
Output
DRAM address output 6.
55
MADRS5
Output
DRAM address output 5.
56
MADRS4
Output
DRAM address output 4.
57
MADRS3
Output
DRAM address output 3.
58
MADRS2
Output
DRAM address output 2.
59
MADRS1
Output
DRAM address output 1.
60
MADRS0
Output
DRAM address output 0.
61
DVDD5
—
Power supply
Internal logic system power supply.
62
VSS
—
GND
63*
STREQ
Input/Output
MP3 stream I/O
MP3 data request flag output.(active high)/DRAM data request flag input.
(CD-ROM mode, active high)
(CD-ROM mode, active high)
64*
STCK
Input/Output
MP3 data transfer clock input/DRAM data transfer clock output.
65*
STDAT
Input/Output
MP3 serial data input/DRAM serial data output.
66
FSYNC
Output
MP3-dec
MP3 data frame sync signal (active high)/Data continuity point detection
complete flag.(CD-DA mode, active high)
complete flag.(CD-DA mode, active high)
67*
CRCF
Output
CD monitor
CRC check result output (CD-ROM data/CD-DA subcode data)/DRAM data
output enable signal output.(active high)
output enable signal output.(active high)
68
DVDD6
—
Power supply
Digital I/O system power supply.
69
VSS
—
GND
70*
WOK
Input
CD-DA shock-
proof and MP3 I/O
proof and MP3 I/O
DRAM write enable input (CD-DA mode, active high)/DRAM data request
flag input.
flag input.
71*
CNTOK
Output
Data continuity point detection complete flag (CD-DA mode, active high)/
SYNC error monitor flag (MP3 mode, active high)/DRAM serial data output.
SYNC error monitor flag (MP3 mode, active high)/DRAM serial data output.
72*
OVF
Output
DRAM write interrupt flag (CD-DA mode, active high)/Emphasis output flag
(CD-DA and MP3 modes, active high)/DRAM data transfer clock output.
(CD-DA and MP3 modes, active high)/DRAM data transfer clock output.
73
CMDOUT
Output
Microcontroller
interface
interface
Serial command data output.(n-channel open-drain output)
74
CMDIN
Input
Serial command data input.
75
CL
Input
Serial command clock input.
76
CE
Input
Command enable input (active high)
77
INTB
Output
Interrupt signal output (active low)/DRAM write interrupt flag. (CD-DA mode,
active high)
active high)
78
RESB
Input
System reset. (active low)
79
DATAIN
Input
CD IF
Serial CD data input.
80
DATACK
Input
CD bit clock input.
XL-HP535H/HP535E
8 – 8
IC3 VHiLC78683E-1: MP3 Decoder (LC78683E)
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LRSY
ADDATA
ADBCK
ADLRCK
C2FIN
TEST1
CKIN
VSS
CKOUT
TEST2
DVDD1
PW
SBSY
SFSY
SBCK
AVDD
VPRFR
VCOC
VPDO
AVSS
DVDD2
VSS
MDATA0
MDATA1
MDATA2
MDATA3
MDATA4
MDATA5
MDATA6
MDATA7
DVDD3
VSS
MDATA8
MDATA9
MDATA10
MDATA11
MDATA12
MDATA13
MDATA14
MDATA15
DATACK
DATAIN
RESB
INTB
CE
CL
CMDIN
CMDOUT
OVF
CNTOK
WOK
VSS
DVDD6
CRCF
FSYNC
STDAT
STCK
STREQ
VSS
DVDD5
MADRS0
MADRS1
MADRS2
MADRS3
MADRS4
MADRS5
MADRS6
MADRS7
VSS
DVDD4
MADRS8
MADRS9
MADRS10
MADRS11
MADRS12
OEB
CASUB
CASLB
WEB
RASB
LC78684
(Top view)
WEB
OEB
CASLB
CASUB
RASB
MADRS[12:0]
MDATA[15:0]
CL
CE
CMDIN
CMDOUT
INTB
STREQ
CKIN
VPRFR
VCOC
VPDO
CKOUT
WOK
CNTOK
OVF
LRSY
DATACK
DATAIN
C2FIN
SFSY
PW
SBSY
SBCK
RESB
STCK
STDAT
CRCF
CRCF
FSYNC
ADLRCK
ADBCK
ADDATA
ADBCK
ADDATA
DRAM-I/F
CD-DA shockproof
(Compressed or
uncompressed)
CDROM
decoder
MP3
decoder
M
U
X
Audio I/F
System
clock-
generator
VCO
+
PLL
CPU-I/F
Data-I/F
Figure 3 BLOCK DIAGRAM OF IC
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