Sharp XL-DAB9H (serv.man3) Service Manual ▷ View online
XL-DAB9H
7 – 4
The HF waveform is normal and the time is displayed nor-
mally, but no sound is produced. Or the sound has drop-
outs.
mally, but no sound is produced. Or the sound has drop-
outs.
(4) PLL system check.
When a disc is loaded, start play operation.
The HF waveform is normal, but the TOC data cannot be read.
Check the PDOUT waveform. (Figure 6)
Check around pins 26~30 on IC801.
Figure 6
T
FDO
PDOUT1
PDOUT0
Stopped
CH1=500 mV
DC 10:1
CH3=1 V
DC 10:1
CH4=1 V
DC 10:1
500 ms/div
(500 ms/div)
NORM:20 kS/s
1
4
3
=Record Length=
Smoothing : ON
CH1 :
0.000 V
CH2 :
0.0 V
Main :
100 K
Zoom :
2 K
Mode : AUTO
Type : EDGE CH2
Delay :
Type : EDGE CH2
Delay :
0.0 ns
Hold off :
0.2 µs
CH3 :
0.00 V
CH4 :
0.00 V
BW : FULL
=Trigger=
=Filter=
=Offset=
CH1
v/DIV
500 mV
500 mV
1999/04/05 17:33:17
(5) Others.
Is pin 35 (C2F) on IC801 "L"?
No
There are too many error flags on a damaged disc which makes
error correction impossible.
error correction impossible.
Yes
1. When playing at normal speed.
Check the peripheral circuit at pin 69 (DOUT) on IC801 and the
waveform (Figure 7).
Check the peripheral circuit at pin 69 (DOUT) on IC801 and the
waveform (Figure 7).
Check again using a known good disc.
If OK, Check the unit.
Figure 7
T
T
DOUT
Stopped
CH1=2 V
DC 10:1
500 ns/div
1999/04/07 09:25:28
(500 ns/div)
NORM:200 MS/s
1
=Record Length=
Smoothing : ON
CH1 :
0.00 V
CH2 :
0.00 V
Main :
1 K
Zoom :
100
Mode : NORMAL
Type : EDGE CH1
Delay :
Type : EDGE CH1
Delay :
2.887 ms
Hold off :
0.2 µs
CH3 :
0.00 V
CH4 :
0.00 V
BW : FULL
=Trigger=
=Filter=
=Offset=
XL-DAB9H
8 – 1
XL-DAB9H
Service Manual
CHAPTER 8.
OTHERS
[1] FUNCTION TABLE OF IC
TUN1 DCEKLV596SJ01: DAB Unit (For U.K.)
TUN1 DCEKLV597SJ01: DAB Unit (Except for U.K.)
1. FS2023 (VOLTERRA) MODULE OVERVIEW
1.1. Intr od uc tio n
The FS2023 (Volterra) module has been developed as an OEM mod-
ule, which will enable low cost Band
/L-Band DAB receivers. All that
is required to produce a low cost Digital Radio is a power source,
antenna, LCD and Keypad. Alternatively the module can be pro-
grammed to operate in ‘slave’ mode under the control of an existing
microcontroller. The module has been designed for use in static, porta-
ble and car audio products.
antenna, LCD and Keypad. Alternatively the module can be pro-
grammed to operate in ‘slave’ mode under the control of an existing
microcontroller. The module has been designed for use in static, porta-
ble and car audio products.
Reference software can be provided for both master (Reference MMI),
or slave (Serial Interface) applications.
or slave (Serial Interface) applications.
1.2. Features
A block diagram of the Module is shown in Figure 7-1. The main com-
ponents are Band
/L-Band RF frontend, FS1010 (Chorus) DAB
baseband processor, a serial boot FLASH and audio DAC.
As an option SDRAM can be fitted to support advanced applications.
External components that may be connected to the module are shown
as grey blocks in Figure 7-1.
External components that may be connected to the module are shown
as grey blocks in Figure 7-1.
NOTE: 3.3 V rail is connected to RF section only and care should be
taken to provide a clean, decoupled supply to ensure that the
RF sensitivity is not degraded.
RF sensitivity is not degraded.
An on-board SPI port supports a serial boot FLASH device.
A dedicated port is provided for direct connection to an LCD, general-
purpose I/O lines are provided for keypad scanning, shaft encoder
input and control of simple circuits.
purpose I/O lines are provided for keypad scanning, shaft encoder
input and control of simple circuits.
Hardware interfaces include USB ports, and a serial host port for con-
nection to a controlling CPU.
nection to a controlling CPU.
Stereo audio output is available in S/PDIF digital formats, as well as
line level. Multi-channel audio output is available via the I
2
S port, while
PCM or compressed audio can be input to CHORUS via the S/PDIF
input.
input.
The FS1010 (Chorus) processor is based around Imagination Technol-
ogies' META advanced RISC/DSP. In addition to running the core DAB
demodulation functions, this processor is well suited to running the
application code, which receiver manufacturers will add on top of the
core DAB processing to produce complete products. The core DAB
functions require less than one third of the processing capacity of
META, leaving considerable scope for application processing.
ogies' META advanced RISC/DSP. In addition to running the core DAB
demodulation functions, this processor is well suited to running the
application code, which receiver manufacturers will add on top of the
core DAB processing to produce complete products. The core DAB
functions require less than one third of the processing capacity of
META, leaving considerable scope for application processing.
2. HARDWARE INTERFACES
The FS2023 (Volterra) module has a number of hardware interfaces,
designed to support a range of DAB applications. The characteristics
of these interfaces are detailed below.
designed to support a range of DAB applications. The characteristics
of these interfaces are detailed below.
2.1. RF Input
There are two connectors available that can be used to carry VHF (174
MHz to 240 MHz) for Band
/1450 MHz to 1492 MHz for L-Band.
These are a 2.6 mm UMP type and 2.54 mm pitch holes to be used
with a header or for direct soldering of an RF cable.
with a header or for direct soldering of an RF cable.
2.2. Analogue Audio output
Stereo line level outputs are provided using the on-board stereo audio
DAC.
DAC.
2.3. Digital Audio Input/Output (I
2
S)
Seven signal wires (master clock, bit clock, sample frame, stereo in, 6
channel out) carry digital audio input and multi-channel output to an
external DAC or CODEC. The multi-channel output may be used for
home cinema applications including Dolby Digital and DTS.
channel out) carry digital audio input and multi-channel output to an
external DAC or CODEC. The multi-channel output may be used for
home cinema applications including Dolby Digital and DTS.
2.4. S/PDIF Audio Output
The S/PDIF audio output carries a stereo digital audio output on a sin-
gle wire using the signal format defined in IEC60958.
gle wire using the signal format defined in IEC60958.
2.5. S/PDIF Input
The S/PDIF input accepts digital audio data on a single wire using the
signal format defined in IEC60958. This input may also be used as an
input for CD-ROM data including MP3 encoded date.
signal format defined in IEC60958. This input may also be used as an
input for CD-ROM data including MP3 encoded date.
2.6. RDI Output
The RDI output carries a an RDI signal conforming to Specification of
the Receiver Data Interface (RDI) - Eureka 147 Project - Issue 1. 4
November 1996 on a single wire using the signal format defined in
IEC60958. If an output is not required, then this line may be used as
GPIO.
the Receiver Data Interface (RDI) - Eureka 147 Project - Issue 1. 4
November 1996 on a single wire using the signal format defined in
IEC60958. If an output is not required, then this line may be used as
GPIO.
Figure 1
VOLTERRA MODULE BLOCK DIAGRAM
(Functions in white are on board, in grey are external)
FS1010
(Chorus)
384KB
RAM
LCD
External
DAC or
CODEC
SDRAM
(optional)
Audio
DAC
Band
/
L-Band RF
3.3V
Serial
Flash
Keypad/
Rotary
encoder
USB
I/face
Serial
I/Faces
S/PDIF
& RDI
I/faces
Input impedance:
50 R, nominal
VSWR
2.0, maximum
Max power:
0 dBm
Sensitivity:
(signal level required for 10
-4
BER with 1/2 rate coding) -98 dBm
Adjacent Channel Rejection
(for 10
-4
BER with 1/2 rate coding)
38 dB minimum
Sample rate:
48 kHz
Master clock rate:
512 x sample rate (24.576 MHz)
Sample resolution:
16, 18, 20 or 24 bits (controlled by software).
Sample rate:
48 kHz
Sample resolution:
24 bits
Sample rate:
48 kHz
RDI format:
high capacity
XL-DAB9H
8 – 2
2.7. Asynchronous Serial Port
The asynchronous serial port carries asynchronous serial characters
over two wires (TxD, RxD) at data rates up to 115 kbit/s. In this particu-
lar application it can be used to control the module in ‘slave’ mode.
The default baud rate is 115 kbit/s.
over two wires (TxD, RxD) at data rates up to 115 kbit/s. In this particu-
lar application it can be used to control the module in ‘slave’ mode.
The default baud rate is 115 kbit/s.
2.8. Universal Serial Bus
A USB 1.1 interface (slave) is carried over two wires. The USB inter-
face will support data transfers at up to 12 Mbits/s.
face will support data transfers at up to 12 Mbits/s.
2.9. Serial Control Bus (I
2
C)
The Serial Control Bus consists of a two wire, open collector bus. This
bus is a master only, and may be used for controlling other devices in
the system.
bus is a master only, and may be used for controlling other devices in
the system.
2.10. PDM output
A single PDM (Pulse Density Modulated) output can be provided for
generation of a low resolution analogue output. This may be used for
control of display brightness for example.
generation of a low resolution analogue output. This may be used for
control of display brightness for example.
2.11. LCD Port
LCD display data is presented on 8 data lines, with 4 timing control
lines to synchronize transfers. The LCD port will support both alphanu-
meric and graphic LCDs. If a LCD connection is not required, then
these lines may be used as GPIO.
lines to synchronize transfers. The LCD port will support both alphanu-
meric and graphic LCDs. If a LCD connection is not required, then
these lines may be used as GPIO.
NOTE: Ideally, the LCD controller should be powered from the 3V3
supply. If a 5 V LCD module is used it should have its own
supply rail and should not be connected to the 5 V RF supply
as any conducted noise will degrade RF sensitivity.
supply rail and should not be connected to the 5 V RF supply
as any conducted noise will degrade RF sensitivity.
2.12. General Purpose I/O
All the above signals (excluding USB, I
2
S control and stereo out) may
be used as GPIO signals. The state of each GPIO signal can be read
by software. The logic level and tri-state drive of each GPIO signal can
also be controlled by software.
by software. The logic level and tri-state drive of each GPIO signal can
also be controlled by software.
The following table specifies the main pin functions, identifies which of
these can be used as GPIO lines, and also defines an example DAB
product function based on the reference MMI software.
these can be used as GPIO lines, and also defines an example DAB
product function based on the reference MMI software.
The Reference MMI software assigns the following button mapping for
the keypad matrix:
the keypad matrix:
Alphanumeric mode: 4-bit or 8-bit data transfers.
Compatible with displays using Hitachi
HD44780, Samsung S6A0069X (KS0066) or
similar controllers.
HD44780, Samsung S6A0069X (KS0066) or
similar controllers.
Graphic mode:
4-bit or 8-bit data transfers.
4 control signals (date clock, line clock, frame
clock, polarity reversal) compatible with wide
range of graphic display controllers.
4 control signals (date clock, line clock, frame
clock, polarity reversal) compatible with wide
range of graphic display controllers.
Main Function
GPIO
CN1 pin
number
Reference MMI
Implementation
S/PDIF Output
A11
12
S/PDIF Output
S/PDIF Input
A0
37
Keypad row 3
RDI Output
A10
38
Keypad row 4
S1_DIN
D3
15
S1_DOUT
D2
16
USB_DP
No
9
USB_DP
USB_DM
No
8
USB_DM
SCP_CLK
A9
39
IR remote activity LED
SCP_DAT
A8
40
IR receiver input
PDM Output
A7
41
Keypad column 3
LCD_DATA<7..0>
B<15..8>
25-32
LCD_DATA<7..0>
LCD_F
C1
33
Keypad row 2
LCD_LRS
C2
34
LCD_RS
LCD_M
C0
35
Keypad row 1
LCD_PE
C3
36
LCD_E
AUD_SFR
No
21
AUD_SFR
AUD_SCLK
No
23
AUD_SCLK
AUD_MCLK
No
24
AUD_MCLK
AUD_SDOUT0
No
22
AUD_SDOUT0
AUD_SDOUT1
A1
42
Keypad column 1
AUD_SDOUT2
A2
43
Keypad column 2
AUD_SDIN
A12
44
Keypad column 4
Column 1
Column 2
Column 3
Column 4
Row 1
scroll_up
scroll_down
Select
preset 1
Row 2
display
info
Scan
preset 2
Row 3
volume_up
volume_down
Mute
preset 3
Row 4
power
factory_rst
preset 4
preset 5
XL-DAB9H
8 – 3
IC601 VHiLC75341M-1: Signal Control (LC75341M)
IC601 VHiLC75341M-1: Signal Control (LC75341M)
Pin No.
Terminal Name
Function
1
DI
Serial data and clock input pin for con-
trol.
trol.
2
CE
Chip enable pin.
Data written into an internal latch in a
timing of "H" to "L".
Each analog switch is activated.
Data transfer enabled at "H" level.
Data written into an internal latch in a
timing of "H" to "L".
Each analog switch is activated.
Data transfer enabled at "H" level.
3
VSS
Ground pin.
4
LOUT
Bass band filter comprising
capacitor and resistor connection pin
and bass/treble output pin.
capacitor and resistor connection pin
and bass/treble output pin.
5
LBASS
Bass band filter comprising capacitor
and resistor connection pin.
and resistor connection pin.
6
LTRE
Treble band filter comprising capacitor
and resistor connection pin.
and resistor connection pin.
7
LIN
Volume + equaliser output pin.
8
LSEL0
Input selector output pin.
9,10,11,
12
12
L4-1
Input signal pin.
Pin No.
Terminal Name
Function
13,14,
15,16
15,16
R1-4
Input signal pin.
17
RSEL0
Input selector output pin.
18
RIN
Volume + equaliser output pin
19
RTRE
Treble band filter comprising capacitor
and resistor connection pin.
and resistor connection pin.
20
RBASS
Bass band filter comprising capacitor
and resistor connection pin.
and resistor connection pin.
21
ROUT
Bass band filter comprising capacitor
and resistor connection pin and bass/
treble output pin.
and resistor connection pin and bass/
treble output pin.
22
VREF
0.5x VDD voltage generation block
for analog ground. Capacitor of sev-
eral 10µF to be connected between
VREF and AWSS (VSS) as a counter-
measure against power ripple.
for analog ground. Capacitor of sev-
eral 10µF to be connected between
VREF and AWSS (VSS) as a counter-
measure against power ripple.
23
VDD
Supply pin
24
CL
Serial data and clock input pin for con-
trol.
trol.
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
17
LVref
RVref
CONTROL
CIRCUIT
LOGIC
CIRCUIT
CONTROL
CIRCUIT
LOUT
LBASS
LIN
LSEL0
L4
L3
L2
L1
R1
R2
R3
R4
RSEL0
RIN
RTRE
LTRE
RBASS
ROUT
VREF
VDD
CL
DI
CE
VSS
CCB
INTERFACE
Figure 2 BLOCK DIAGRAM OF IC
Click on the first or last page to see other XL-DAB9H (serv.man3) service manuals if exist.