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Model
XL-65H (serv.man19)
Pages
7
Size
72.82 KB
Type
PDF
Document
Service Manual
Brand
Device
Audio / System / Function table of IC
File
xl-65h-sm19.pdf
Date

Sharp XL-65H (serv.man19) Service Manual ▷ View online

XL-55H/65H
– 48 –
IC801 VHiMN6627482W: Servo/Signal Control (MN6627482W) (2/2)
Terminal Name
Pin No.
Input/Output
Function
47
DSLF
Input/Output
DSL loop filter terminal.
48
PLLF
Input/Output
PLL loop filter terminal.
49
VCOF
Input/Output
VCO loop filter terminal.
50
AVDD2
Input
Analog circuit power supply. (DSL, PLL and DA output sections for AD)
51
AVSS2
Input
Analog circuit GND. (DSL, PLL and DA output sections for AD)
52*
EFM, CK384
Output
· IOSEL=H: EFM signal output.
· IOSEL=L: X-tal system 16.9344 MHz clock output.
Signal processing system: 384fs output. (VCO clock for jitter-free operation)
(X-tal system or signal processing system can be selected by the command.)
53
PCK, DSLB
Output
PLL extraction clock output or DSL balance output. fPCK-4.3218 MHz
54
VCOF2
Input/Output
Loop filter terminal for digital servo 33.8688 MHz creation VCO.
X-tal 16.9344 MHz: external circuit is needed.
55*
SUBC
Output
Subcode serial output. CD-TEXT mode 1: TEXT data output.
56*
SBCK
Input
Subcode serial output clock input. CD-TEXT mode 1: TEXT data read clock input
57
VSS
Input
Oscillation circuit GND.
58
X1
Input
Oscillation circuit input terminal. f=16.9344 MHz, 33.8688 MHz
59
X2
Output
Oscillation circuit output terminal. f=16.9344 MHz, 33.8688 MHz
60
VDD
Input
Oscillation circuit power supply.
61*
BYTCK, TRVSTP
Output
IOSEL=H: byte clock signal output.
IOSEL=L: traverse STOP signal output. H: STOP Mode
62*
GIO1, /CLDCK
Output
Default: general purpose I/O port.
Command execution: terminal for subcode frame clock signal output. (fCLDCK=7.35 kHz)
63*
GIO2, FCLK
Output
Default: general purpose I/O port.
Command execution: crystal frame clock signal output. (fFCLK=7.35 kHz)
64*
IPFLAG
Output
Interpolation flag signal output. H: Interpolation
65*
FLAG
Output
Flag signal output.
66*
CLVS
Output
Output for spindle servo phase synchronization signal. H: CLV, L: Rough servo
67*
CRC
Output
Default: output for subcode CRC check results. H: OK, L: NG
68*
DEMPH
Output
Demphasis detection signal output. H: ON
69*
RESY, FLAG6
Output
IOSEL= H: resync signal RESY output for frame synchronization.
H: Synchronization, L: Synchronization lost
IOSEL=L: RAM address reset signal for error correct deinterleave.
FLAG 6 output L: Address reset
70
IOSEL
Input
Mode switch terminal.
71
/TEST
Input
Test terminal. Normal: H
72
AVDD1
Input
Analog circuit power supply. (Audio output section (for both Lch and Rch))
73
OUTL
Output
Lch audio output.
74
AVSS1
Input
Analog circuit GND. (Audio output section (for both Lch and Rch))
75
OUTR
Output
Rch audio output.
76
RSEL, GIO3
Input
Default: RF signal polarity specification terminal.
Brightness H: RESEL=H
Brightness L: RESEL=L
Command execution: general purpose I/O port.
RF signal polarity can be specified by command.
CD-TEXT mode 1 or 2: TEXT data read enabling signal (DQSY) output
77
CSEL
Input
Oscillation frequency specification terminal.
H: Oscillation frequency=33.8688 MHz L: Oscillation frequency=16.9344 MHz
78
PSEL
Input
IOSEL=H: test terminal. (Normal: L)
IOSEL=L: SRDATA input.
79
MSEL
Input
IOEL=H: SMCK terminal output, frequency switch terminal.
H: SMCK=8.4672 MHz
L: SMCK=4.2336 MHz
IOSEL=L: LRCK input
H: Lch data, L: Rch data
SMCK=4.2336 MHz fixed
80
SSEL
Input
IOSEL=H: switch terminal for SUBQ terminal output mode.
H: Q code buffer mode
L: CLDCK synchronization mode
IOSEL=L: BCLK input
Q code buffer mode fixed
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
– 49 –
XL-55H/65H
IC801 VHiMN6627482W: Servo/Signal Control (MN6627482W)
STAT
X1
X2
MSEL
CSEL
PMCK(PLAY)
GIO2(FCLK)
SMCK
BYTCK(TRVSTP)
VCOF
VCOF2
MDATA MCLK MLD
PSEL RSEL(GIO3) ARF DRF I
REF
DSLF PLLF2 PLLF EFM(CK384) PCK(DSLB) AV
DD2
AV
SS2
SUBQ SOCK(GIO0) SSEL
FLAG6(RESY)
IOSEL
DEMPH
SUBC
SBCK
GIO1(/CLDCK)
BLKCK
CRC
CLVS
SRDATAIN(PSEL) BCLKIN(SSEL) LRCKIN(MSEL)
V
DD
V
SS
DV
DD1
DV
SS1
/RST
/TEST
FE
RFENV
TE
TRCRS
BDO
VDET
/RFDET
OFT
SENSE
WVEL
LDON
/FLOCK /TLOCK
FBAL TBAL FOD TRD
TVD
VREF
TRV
KICK
TOFS
DMUTE
BCLK
SRDATA
LRCK
OUTR AV
DD1
AV
SS1
OUTL
IPFLAG
FLAG
PC
ECS
ECM
TIMING
GENERATOR
PITCH CONTROL
MICRO
COMPUTER
INTERFACE
SERVO
CPU
A/D CONVERTER
INPUT PORT
SERVO TIMING
GENERATOR
VCO
OUTPUT PORT
D/A
CONVERTER
INTER
POLATION
SOFT MUTING
DIGITAL
ATTENUATION
CLV
SERVO
DIGITAL
AUDIO
INTERFACE
16k
SRAM
PWM
(L)
PWM
(R)
1 BIT DAC
PWMLOGIC
8TIMES
OVER
SAMPLING
DIGITAL FILTER
DIGITAL
DEEMPHSIS
DSL • PLL VCO
SUBCODE
BUFFER
EFM    DEMODULATION
SYNC  INTERPOLATION
SUBCODE    DEMODULATION
CD-TEXT
BUFFER
CIRC ERROR CORRECTION
DEINTERLEAVE
-
+
-
+
TX
Figure 49 BLOCK DIAGRAM OF IC
XL-55H/65H
– 50 –
IC802 VHiAN22000A-1: Head Amp. (AN22000A)
1
PD
APC amp input.
2
LD
APC amp output.
3
VCC
Power supply.
4
RFN
RF amp inverting input.
5
RFOUT
RF addition amp output.
6
RFIN
AGC amp input.
7
CAGC
AGC loop filter connection.
8
ARF
AGC output.
9
CEA
Capacitor for HPF-amp connection.
10
3TOUT
3T-ENV output.
11
CBDO
Capacitor for RF dark-side envelope detection connection.
12
BDO
BDO output.
13
COFTR
Capacitor for RF bright-side envelope detection connection.
14
OFTR
OFTR output.
15
NRFDET
NRFDET output.
16
GND
Ground
17
VREF
VREF output.
18
VDET
VDET output.
19
TEBPF
VDET input.
20
TEOUT
TE amp output.
21
TEN
TE amp inverting input.
22
FEN
FE amp inverting input.
23
FEOUT
FE amp output.
24
GCTL
Gain & APC control.
25
FBAL
FBAL control.
26
TBAL
TBAL control.
27
E
Tracking signal input 1.
28
F
Tracking signal input 2.
29
D
Focus signal input 4.
30
B
Focus signal input 2.
31
C
Focus signal input 3.
32
A
Focus signal input 1.
Pin No.
Function
Terminal Name
Figure 50 BLOCK DIAGRAM OF IC
A
C
B
D
F
VREF
E
32
28
17
27
29
30
31
24
3
16
25
26
1
19
20
10
9
15
22
23
21
18
2
4
14
13
12
11
8
7
6
5
RFN
RFOUT
RF_EQ
AGC
BDO
NRFDET
OFTR
3TENV
CAGC
ARF
CBD0
BD0
COFTR
OFTR
CEA
3TOUT
NRFDET
FEN
FEOUT
TEN
TEOUT
TEBPF
VDET
VCC
GND
PD
LD
FBAL
GCTL
TBAL
+
-
+
-
+
-
+
-
VDET
SUBT
SUBT
AMP
GCA
BCA
AMP
GCA
BCA
AMP
GCA
BCA
AMP
GCA
BCA
RFIN
XL-55H/65H
– 50 –
IC802 VHiAN22000A-1: Head Amp. (AN22000A)
1
PD
APC amp input.
2
LD
APC amp output.
3
VCC
Power supply.
4
RFN
RF amp inverting input.
5
RFOUT
RF addition amp output.
6
RFIN
AGC amp input.
7
CAGC
AGC loop filter connection.
8
ARF
AGC output.
9
CEA
Capacitor for HPF-amp connection.
10
3TOUT
3T-ENV output.
11
CBDO
Capacitor for RF dark-side envelope detection connection.
12
BDO
BDO output.
13
COFTR
Capacitor for RF bright-side envelope detection connection.
14
OFTR
OFTR output.
15
NRFDET
NRFDET output.
16
GND
Ground
17
VREF
VREF output.
18
VDET
VDET output.
19
TEBPF
VDET input.
20
TEOUT
TE amp output.
21
TEN
TE amp inverting input.
22
FEN
FE amp inverting input.
23
FEOUT
FE amp output.
24
GCTL
Gain & APC control.
25
FBAL
FBAL control.
26
TBAL
TBAL control.
27
E
Tracking signal input 1.
28
F
Tracking signal input 2.
29
D
Focus signal input 4.
30
B
Focus signal input 2.
31
C
Focus signal input 3.
32
A
Focus signal input 1.
Pin No.
Function
Terminal Name
Figure 50 BLOCK DIAGRAM OF IC
A
C
B
D
F
VREF
E
32
28
17
27
29
30
31
24
3
16
25
26
1
19
20
10
9
15
22
23
21
18
2
4
14
13
12
11
8
7
6
5
RFN
RFOUT
RF_EQ
AGC
BDO
NRFDET
OFTR
3TENV
CAGC
ARF
CBD0
BD0
COFTR
OFTR
CEA
3TOUT
NRFDET
FEN
FEOUT
TEN
TEOUT
TEBPF
VDET
VCC
GND
PD
LD
FBAL
GCTL
TBAL
+
-
+
-
+
-
+
-
VDET
SUBT
SUBT
AMP
GCA
BCA
AMP
GCA
BCA
AMP
GCA
BCA
AMP
GCA
BCA
RFIN
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