Sharp XL-55 (serv.man19) Service Manual ▷ View online
XL-55H/65H
– 46 –
IC701 RH-iX0060SJZZ: System Control Microcomputer (IX0060SJ) (2/2)
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I
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O
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S
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S
S
S
S
S
S
S
S
S
S
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
O
O
O
O
O
O
O
O
O
O
S
S
S
S
S
S
S
S
S
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S
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S
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S
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S
COM3
COM2
COM1
COM0
COM2
COM1
COM0
VLC3
VLC2
VLC1
VLC2
VLC1
VDD
OSC2
OSC1
OSC1
VSS
XI
XO
MMOD
VREF-
CLID_SW
KEY1
KEY2
KEY2
MODEL
CLID_PRO
CD_CONF
TAPE_SW
TAPE_SW
VSM
VREF+
DI
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
MCLK
MLD
MDATA
BLKCK
STAT
CD_STB
MRST
PU-IN
FAN
AMP_DEC
SP_DEC
B-LIGHT
DO
CL
CE
SOL
MOT
REC
RESET
GVSW
RUN_PLS
BIAS
B-CAN
POWER
SYS STOP
REMOCON
CLE
JOG UP
JOG DOWN
SURR
P-STB
P-MUTE
CD+B
P-CONT
DATA
STEREO
SD
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
Figure 46 BLOCK DIAGRAM OF IC
Function
Terminal Name Input/Output
54*
SEG46 P63/A3
Output
Power IC amplifier detect.
55*
SEG45 P64/A4
Output
Fan control.
56*
SEG44 P65/A5
Output
57*
SEG43 P66/A6
Output
58
SEG42 P67/A7
Input
CD pickup position detection SW input. "L" = Innerst periphery
59
SEG41 P70/A8
Output
Reset signal output for MN8827482W
60
SEG40 P71/A9
Output
ON/OFF output terminal of CD servo control IC. "H" = Servo ON, "L" = Servo stand-by
61-64
SEG39 P72/A10- Input/Output
Data input/output terminal for MN8827482W control.
SEG36 P75/A13
65
SEG35 P76/A14
Output
Data synchronous clock output for MN8827482W.
66*
SEG34 P77/A15
Output
Chip enable terminal for MN8827482W. "L" = BUS terminal active
67
SEG33 P87/D7
—
LCD segment output.
68
SEG32 P86/D6
—
LCD segment output.
69-74
SEG31 P85/D5-
—
LCD segment output
SEG26 P80/D0
75-100
SEG25-SEG0
—
LCD segment output
Pin No.
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
– 47 –
XL-55H/65H
IC801 VHiMN6627482W: Servo/Signal Control (MN6627482W) (1/2)
1*
BCLK
Output
SRDATA bit clock output.
2*
LRCK
Output
L/R identification signal output.
3*
SRDATA
Output
Serial data output.
4
DVDD1
Input
Digital circuit power supply.
5
DVSS1
Input
Digital circuit GND.
6
TX
Output
Digital audio interface output signal.
7
MCLK
Input
Microcomputer command clock signal input. (Data latch at the rising edge.)
8
MDATA
Input
Microcomputer command data input.
9
MLD
Input
Microcomputer command load signal input. L: Load
10*
SENSE
Output
Sense signal output. (OFT, FESL, NACEND, NAJEND, SFG)
11*
/FLOCK
Output
Focus servo lead-in signal. (L: Lead-in)
12*
/TLOCK
Output
Tracking servo lead-in signal. (L: Lead-in)
13
BLKCK
Output
Subcode block clock signal. (fBLKCK=75 Hz)
14
SQCK, GIO0
Input
Default: external clock input for subcode Q resistor.
Command execution: general purpose I/O port.
CD-TEXT mode 2: TEXT data read clock input.
Command execution: general purpose I/O port.
CD-TEXT mode 2: TEXT data read clock input.
15*
SUBQ
Output
Subcode Q data output.
CD-TEXT mode 2: TEEXT data output.
CD-TEXT mode 2: TEEXT data output.
16
DMUTE
Input
Muting input. (Effective only at bit rate 64fs output.) H: Mute
17
STAT
Output
Status signal. (CRC, STCNT, CLVS, TTSTOP, JCLVS, SQOK, FLAG6, SENE, FLOCK,
TLOCK, revolving speed data, FCLV, SUBQ, SYFLG)
CD-TEXT mode 3: subcode Q and TEXT data output.
TLOCK, revolving speed data, FCLV, SUBQ, SYFLG)
CD-TEXT mode 3: subcode Q and TEXT data output.
18
/RST
Input
Reset input (L: Reset)
19*
SMCK
Output
MSEL=H: 8.4672 MHz clock signal output.
MSEL=L: 4.2336 MHz clock signal output.
MSEL=L: 4.2336 MHz clock signal output.
20*
PMCK, PLAY
Output
Default: 88.2 kHz clock signal output.
Command execution: Play signal output. H: play
Command execution: Play signal output. H: play
21
TRV
Output
Traverse forcing transmission output. 3-State
22
TVD
Output
Traverse drive output.
23*
PC
Output
Spindle motor ON output. L: ON (Default)
24
ECM
Output
Spindle motor drive signal. (Forcing mode output.) 3-State
25
ECS
Output
Spindle motor drive signal. (Servo error signal output.)
26
KICK
Output
Kick pulse output. 3-State
27
TRD
Output
Tracking drive output.
28
FOD
Output
Focus drive output.
29
VREF
Input
DA output section (TVD, ECS, TRD, FOD, FBAL, TBAL, TOFS) reference voltage.
30
FBAL
Output
Focus balance adjustment output.
31
TBAL
Output
Tracking balance adjustment output.
32
FE
Input
Focus error signal input. (Analog input)
33
TE
Input
Tracking error signal input. (Analog input)
34
RFENV
Input
RF envelope signal input. (Analog input)
35
VDET
Input
Oscillation detection signal input. H: Detection
36
OFT
Input
Off track signal input. H: Off track
37
TRCRS
Input
Track cross signal input. (Analog input)
38
/RFDET
Input
RF detection signal input. L: Detection
39
BDO
Input
Drop out signal input. H: Drop out
40
LDON
Output
Laser ON signal output. H: ON
41
PLLF2
Input/Output
Loop filter characteristic switch terminal for PLL.
42*
TOFS
Output
Tracking offset adjustment output. (Shared with general purpose DA output terminal.)
43*
WVEL
Output
Double-speed status signal output. H: Double-speed
44
ARF
Input
RF signal input.
45
IREF
Input
Reference current input terminal
46*
DRF
Input
DSL bias terminal.
Terminal Name
Pin No.
Input/Output
Function
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
XL-55H/65H
– 48 –
IC801 VHiMN6627482W: Servo/Signal Control (MN6627482W) (2/2)
Terminal Name
Pin No.
Input/Output
Function
47
DSLF
Input/Output
DSL loop filter terminal.
48
PLLF
Input/Output
PLL loop filter terminal.
49
VCOF
Input/Output
VCO loop filter terminal.
50
AVDD2
Input
Analog circuit power supply. (DSL, PLL and DA output sections for AD)
51
AVSS2
Input
Analog circuit GND. (DSL, PLL and DA output sections for AD)
52*
EFM, CK384
Output
· IOSEL=H: EFM signal output.
· IOSEL=L: X-tal system 16.9344 MHz clock output.
Signal processing system: 384fs output. (VCO clock for jitter-free operation)
(X-tal system or signal processing system can be selected by the command.)
· IOSEL=L: X-tal system 16.9344 MHz clock output.
Signal processing system: 384fs output. (VCO clock for jitter-free operation)
(X-tal system or signal processing system can be selected by the command.)
53
PCK, DSLB
Output
PLL extraction clock output or DSL balance output. fPCK-4.3218 MHz
54
VCOF2
Input/Output
Loop filter terminal for digital servo 33.8688 MHz creation VCO.
X-tal 16.9344 MHz: external circuit is needed.
X-tal 16.9344 MHz: external circuit is needed.
55*
SUBC
Output
Subcode serial output. CD-TEXT mode 1: TEXT data output.
56*
SBCK
Input
Subcode serial output clock input. CD-TEXT mode 1: TEXT data read clock input
57
VSS
Input
Oscillation circuit GND.
58
X1
Input
Oscillation circuit input terminal. f=16.9344 MHz, 33.8688 MHz
59
X2
Output
Oscillation circuit output terminal. f=16.9344 MHz, 33.8688 MHz
60
VDD
Input
Oscillation circuit power supply.
61*
BYTCK, TRVSTP
Output
IOSEL=H: byte clock signal output.
IOSEL=L: traverse STOP signal output. H: STOP Mode
IOSEL=L: traverse STOP signal output. H: STOP Mode
62*
GIO1, /CLDCK
Output
Default: general purpose I/O port.
Command execution: terminal for subcode frame clock signal output. (fCLDCK=7.35 kHz)
Command execution: terminal for subcode frame clock signal output. (fCLDCK=7.35 kHz)
63*
GIO2, FCLK
Output
Default: general purpose I/O port.
Command execution: crystal frame clock signal output. (fFCLK=7.35 kHz)
Command execution: crystal frame clock signal output. (fFCLK=7.35 kHz)
64*
IPFLAG
Output
Interpolation flag signal output. H: Interpolation
65*
FLAG
Output
Flag signal output.
66*
CLVS
Output
Output for spindle servo phase synchronization signal. H: CLV, L: Rough servo
67*
CRC
Output
Default: output for subcode CRC check results. H: OK, L: NG
68*
DEMPH
Output
Demphasis detection signal output. H: ON
69*
RESY, FLAG6
Output
IOSEL= H: resync signal RESY output for frame synchronization.
H: Synchronization, L: Synchronization lost
IOSEL=L: RAM address reset signal for error correct deinterleave.
FLAG 6 output L: Address reset
H: Synchronization, L: Synchronization lost
IOSEL=L: RAM address reset signal for error correct deinterleave.
FLAG 6 output L: Address reset
70
IOSEL
Input
Mode switch terminal.
71
/TEST
Input
Test terminal. Normal: H
72
AVDD1
Input
Analog circuit power supply. (Audio output section (for both Lch and Rch))
73
OUTL
Output
Lch audio output.
74
AVSS1
Input
Analog circuit GND. (Audio output section (for both Lch and Rch))
75
OUTR
Output
Rch audio output.
76
RSEL, GIO3
Input
Default: RF signal polarity specification terminal.
Brightness H: RESEL=H
Brightness H: RESEL=H
Brightness L: RESEL=L
Command execution: general purpose I/O port.
RF signal polarity can be specified by command.
CD-TEXT mode 1 or 2: TEXT data read enabling signal (DQSY) output
RF signal polarity can be specified by command.
CD-TEXT mode 1 or 2: TEXT data read enabling signal (DQSY) output
77
CSEL
Input
Oscillation frequency specification terminal.
H: Oscillation frequency=33.8688 MHz L: Oscillation frequency=16.9344 MHz
H: Oscillation frequency=33.8688 MHz L: Oscillation frequency=16.9344 MHz
78
PSEL
Input
IOSEL=H: test terminal. (Normal: L)
IOSEL=L: SRDATA input.
IOSEL=L: SRDATA input.
79
MSEL
Input
IOEL=H: SMCK terminal output, frequency switch terminal.
H: SMCK=8.4672 MHz
H: SMCK=8.4672 MHz
L: SMCK=4.2336 MHz
IOSEL=L: LRCK input
H: Lch data, L: Rch data
SMCK=4.2336 MHz fixed
H: Lch data, L: Rch data
SMCK=4.2336 MHz fixed
80
SSEL
Input
IOSEL=H: switch terminal for SUBQ terminal output mode.
H: Q code buffer mode
H: Q code buffer mode
L: CLDCK synchronization mode
IOSEL=L: BCLK input
Q code buffer mode fixed
Q code buffer mode fixed
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
– 49 –
XL-55H/65H
IC801 VHiMN6627482W: Servo/Signal Control (MN6627482W)
STAT
X1
X2
MSEL
CSEL
PMCK(PLAY)
GIO2(FCLK)
SMCK
BYTCK(TRVSTP)
VCOF
VCOF2
MDATA MCLK MLD
PSEL RSEL(GIO3) ARF DRF I
REF
DSLF PLLF2 PLLF EFM(CK384) PCK(DSLB) AV
DD2
AV
SS2
SUBQ SOCK(GIO0) SSEL
FLAG6(RESY)
IOSEL
DEMPH
SUBC
SBCK
GIO1(/CLDCK)
BLKCK
CRC
CLVS
SRDATAIN(PSEL) BCLKIN(SSEL) LRCKIN(MSEL)
V
DD
V
SS
DV
DD1
DV
SS1
/RST
/TEST
FE
RFENV
TE
TRCRS
BDO
VDET
/RFDET
OFT
SENSE
WVEL
LDON
/FLOCK /TLOCK
FBAL TBAL FOD TRD
TVD
VREF
TRV
KICK
TOFS
DMUTE
BCLK
SRDATA
LRCK
OUTR AV
DD1
AV
SS1
OUTL
IPFLAG
FLAG
PC
ECS
ECM
TIMING
GENERATOR
PITCH CONTROL
GENERATOR
PITCH CONTROL
MICRO
COMPUTER
INTERFACE
SERVO
CPU
A/D CONVERTER
INPUT PORT
SERVO TIMING
GENERATOR
VCO
OUTPUT PORT
D/A
CONVERTER
INTER
POLATION
SOFT MUTING
DIGITAL
ATTENUATION
CLV
SERVO
DIGITAL
AUDIO
INTERFACE
16k
SRAM
PWM
(L)
PWM
(R)
1 BIT DAC
PWMLOGIC
8TIMES
OVER
SAMPLING
DIGITAL FILTER
DIGITAL
DEEMPHSIS
DSL • PLL VCO
SUBCODE
BUFFER
EFM DEMODULATION
SYNC INTERPOLATION
SUBCODE DEMODULATION
CD-TEXT
BUFFER
CIRC ERROR CORRECTION
DEINTERLEAVE
-
+
-
+
TX
Figure 49 BLOCK DIAGRAM OF IC
Display
