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– 17 –

The analog signals input from CNPA1 and CNPA2 are input from the terminals 17 and 20 of ICA1. At the input step of ICA1,
the signal input signal is regarded as the differential input signal, and the switching signal which is later called "dynamic
feedback" is attenuated and is regarded as the level-shifted negative feedback signal.
They are added, and is transmitted to the differential type primary integrator of the 

 modulation 1-bit conversion circuit.

After they are integrated by the 2nd to 7th order integrator group, the integrated values of 2nd to 7th are added with the adder.
The added result is compared with Vdd/2 (=2.5 V) by the comparator, and is quantized. As the result, the 1-bit signal is gained.
Since the 

 modulation circuit operates at 128fs (= 5.6448 MHz, fs = 44.1 kHz), the 1-bit signal exceeds the limit of the

switching speed of the power MOS-FET which is the switching element of the switching circuit of the later step.
Therefore, the signal is passed through the double width conversion circuit which doubles the pulse width to 64fs, and is output
from the terminals 2, 3, 5 and 6.
After the limiter is applied to the digital signal input from CNPA3 and CNPA4 at ZDA81 to ZDA84, it is directly transmitted to
the differential type primary integrator of the 

 modulation circuit from the feedback terminals 14, 15, 22 and 23. The signal

process hereafter is the same as that of the analog signal.

The output signal of ICA1 is distributed to FET driver IC for the full bridge in the switching circuit by ICA2 and ICA3 of the logic
circuit IC.

Though the output is L (0 V) or H (5 V) in ICA2 and ICA3, they shift the level from the reference voltage -32 V of the FET driver
IC to L (-32 V) and H (-22 V) with QA1 to QA8 and 1 kohms (RA45 to RA52) and 390 ohms (RA37 to RA44), and it is used as
the FET drive signal.

In the bridge circuit composed using the N channel power MOS-FET, the source of the power MOS-FET of the high side
fluctuates in the potential in the output state, being the floating drive type.
Accordingly, the auxiliary power supply to supply the power to the gate becomes necessary. Here, the boot strap circuit is used
as the auxiliary power supply.
When H (-22 V) is supplied to the terminal No. 6 of FET driver IC (ICA4 to ICA7), the terminal No. 8 is driven to turn on FET
of the low side. As shown in the illustration of the boot strap circuit, the current 

1

 flows, and the electric charge is accumulated

in the boot strap capacitor C. In the practical circuit, it corresponds to CA36 to CA39 connected to the terminal 2.
When H (-22 V) is applied to the terminal 5, the terminal 3 is driven to turn on FET of the high side.
At this time, the electric charge accumulated at 

1

 is discharged, and the current 

2

 flows to charge Cgs of FET as shown in

the illustration of the boot strap circuit.

+32 V and -32 V are switched with the power MOS-FET (QA9 to QA16).
(When the impedance switch is a 4 ohms load, +24 V and -24 V are applied.)

From the signal switched by the power switch circuit, the analog signal is picked out by the low pass filter composed of the 4th
order Butterworth type of the cutoff frequency 100 kHz.

The signal which is switched with the power switching circuit is divided by the resistors of the fixed type of 6.8 kohms (RA101,
RA102), semi-fixed type of 200 ohms (VRA1, VRA2) and the fixed type of 680 ohms (RA61 and RA62) on the variable side and
the fixed type of 6.8 kohms (RA103 and RA104) and the fixed type of 750 ohms (RA63 and RA64), and is attenuated to +5 V,
0 V.
RLYA1 turns on the relay when the impedance switch is a 8 ohms load to change the resistance division ratio.
The attenuated +5 V, 0 V signal is shifted to the level of Vdd/2 of the terminals 18 and 19 through the resistor (RA91 to RA94),
and is input to the feedback terminals 14, 15, 22 and 23 as the signal of +2.5 V and -2.5 V.

– 18 –

14/23

17/20

IN

15/22

NF(+)
NF(–)

-1

-1

Integrator/Adder 

Group

Comparator

Double width 

conversion

Input Step

Vs

1

2

4

Q

1

Q

2

C

R

i

i

C

GS

X

point

Y point

Diode prevents
i 

2

 from 

returning to Vs.

Q2 is turned on, 
and the holding 
gate voltage is 
gained from C. 
It is necessary to 
periodically 
charge C.

When the protect circuit is activated, the speaker relays RLY107 and RLY108 and the power relay RLY106 are turned off, and
the function switch key is not received.
When the power switch is turned off, it is once reset.
For detection, the overcurrent detection circuit and the output offset detection circuit are provided and the relays and so on are
controlled by the microcomputer.

If any overcurrent flows in R256, the potential difference will be generated both ends of R256 to supply it to Pins 2 and 3 of IC201.
If the output signal from Pin 1 of the output of IC201 is supplied to the comparator IC201 (Pins 5 to 7) (through the time constant
circuit) and reaches the level of the specified value or more, the comparator will be activated to set H at Pin 7. Then, the
transistors Q201 and Q202 will be turned on, and the signal of H level will be supplied to Pin 27 of the microcomputer IC904.
Thus, the protect will be activated.

If any potential difference is generated between the terminals of the speaker (L+ and L- as an example), the potential which
drives Q651 and Q653 will stand at the terminal connected section of the emitter of Q651 or the base of Q653, and either will
be turned on. (Pin 1 of IC651 as reference)
(If + level is established, Q653 will be turned on, and if - level is established, Q651 will be turned on.)
If Q651, Q653 or Q652, Q654 are turned on, Q201 will be activated like the said current detection to supply the signal of H level
to Pin 27 of the microcomputer IC904.

– 19 –

4

1

3

2

5

6

7

8

From OFF-SET Detection Section

R256
Detection 
Resistor

R228

10K

(VRN)

R227
100K

(VRN)

C614

0.01

R202

47K

(VRN)

C201

0.01

Q202

2SC2412 KR

Q210

2SC2412 KR

Q208

2SC2412 KR

D202

DA119

R203
100K

(VRN)

R204

10K

(VRN)

R233
100K

R206
100K

(VRN)

D203

DA119

R205

10K

(VRN)

Q201

2SA1037 KR

R201
100K

(VRN)

D204

DA119 

D206

DA119 

R214

10K

(VRN)

R213

10K

(VRN)

R211

4.7K

(VRN)

R210

47K

(VRN)

R209

4.7K

(VRN)

R208

4.7K

(VRN)

C205

0.01

C204

0.01

C203

0.01

C219

10/25

R212

4.7K

(VRN)

C218

10/25

R180

2.7K

(VRN)

R179
100K

(VRN)

Q116
2SC2412KR

D107

DA119

RLY106

R207

47K

(VRN)

C202

0.01

C313

0.01

R217
100K

(VRN)

C207

0.01

To 

µ

-com

CNP106 Pin 12

IC904

Pin 27

+

–

+

–

MAIN PWB-A1(3/3)

1

4

3

2

7

5

6

8

C655

0.01

C654

0.01

R659

47K

R658

22K

R657

22K

R661

10K

C653

47/50

IC651

NJM4558M

MOTOR DRIVER

+32V

+B

MAIN-A

+15V

–15V

–32V

+32V

R660

4.7K

R652

15K

R654

15K

R656

10K

C652

33/50

D652

DA119

D651

DA119

R653

15K

R651

15K

C651

33/50

R655

10K

Q652

2SC2412KR

Q653

2SC2412KR

Q651

2SC2412KR

Q654

2SC2412KR

–15V

–B

–B

–B

–B

–B

+B

–32V

+15V

+B

+B

+B

P39  9 - H,12 - C,12 - G

TO MAIN SECTION

L+

L–

R+

R–

A

3
4
6
5

B
C
E

D

– 20 –

1 

- - 

+ + 

+ + 

- - 

Check the wiring process.

Any lead CNP101 (4P), CNP102 (3P) or CMP109 (6P) 
does not interfere with the cement resistor or heat sink plate.  

CNP109

Heat Sink

Cement 
Resistor

The cement resistor falls down 90 degrees toward the chassis.

On CNP101(4P) and CNP102(3P) leads, the sag is processed on the 
new panel side to avoid the cement resistor.

The sag of CNP101(4P) and CNP102(3P) is
processed with the nylon band bundle.

Nylon Band

Line process clamper

Side view of bottom chassis

Pin 9 lead form the 1-bit unit is inserted to
(CNP109), and the sag of the lead is
processed as shown.

Pin 9 lead form the 1-bit unit is inserted to
(CNP109), and the sag of the lead is
processed as shown.

Pin 9 Lead

CNP109

Pin 9 Lead

CNP109

or

Pin 3 lead from the 1-bit unit is inserted to the upper clamp of the 
power shield, and Pin 4 lead is inserted to the lower clamp.

CNP101

CNP102

1

1

1

1

-

+

-

+

1

-

+

-

+

Press SP lead into the clearance between 
case and PWB along the chassis.
Collect the sag of the lead toward the arrow 
side.
It must not interfere with the lag set screw of 
A section.

When processing the line, recheck whether 
the lead from 1 bit (3 places) and the lead 
connector from the main volume are securely 
pushed in.

Press it into the clearance between 
PWB and case. CNP107 and CNP108 
leads must be present on the volume lead.

Nylon Band

CNP109

Pin 9 Lead

Nylon Band

Pin 9 Lead

CNP109

Reinsert Pin 9 lead from 1 bit to (CNP109), 
process the sag of the lead as shown, and 
insert the nylon band into the digital PWB hole. 
Then, bundle it. 
After processing, push in the lead under the 
PWB (arrow direction).
After processing the line, check whether 
CNP109 gets off or not.

Reinsert Pin 9 lead from 1 bit to (CNP109), 
process the sag of the lead as shown, and 
insert the nylon band into the digital PWB hole. 
Then, bundle it.
After processing, push in the lead under the 
PWB (arrow direction).
After processing the line, check whether
CNP109 gets off or not.

or

A

1BIT UNIT

Nylon
Band

CNP601

Bundle the main volume lead on 
the main volume hardware as shown.
After bundling, verify that CNP601 
does not get off.

Insert pin 3 lead from 1 bit to the 
free line process clamp on the 
upper part of the power shield.