Sharp SD-EX220 (serv.man2) Service Manual ▷ View online
SD-EX220H
8 – 4
IC101 VHiCS4340KS-1: DAC IC (CS4340KS) (1/2)
1
RST
Input
Reset
The device enters a low power mode and all internal state machines are reset to the default
settings when low. RST should be held low during power-up until the power supply, master
and left/right clocks are stable.
The device enters a low power mode and all internal state machines are reset to the default
settings when low. RST should be held low during power-up until the power supply, master
and left/right clocks are stable.
2
SDATA
Input
Serial Audio Data
Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA
via the serial clock and the channel is determined by the Left/Right clock.
The required relationship between the Left/Right clock, serial clock and serial data is defined
by the DIF1-0 pins.
Two's complement MSB-first serial data is input on this pin. The data is clocked into SDATA
via the serial clock and the channel is determined by the Left/Right clock.
The required relationship between the Left/Right clock, serial clock and serial data is defined
by the DIF1-0 pins.
3
SCLK
Input
Serial Clock
Clocks the individual bits of the serial data into the SDATA pin.
The required relationship between the Left/Right clock, serial clock and serial data is defined
by the DIF1-0 pins.
The CS4340 supports both internal and external serial clock generation modes.
Internal SCLK mode is used to gain access to extra de-emphasis modes.
Internal Serial Clock Mode
In the internal Serial Clock Mode, the serial clock is internally derived and synchronous with
the master clock and left/right clock.
The SCLK/LRCK frequency ratio is either 32, 48 or 64 depending upon the DIF1-0 pins.
Operation in this mode is identical to operation with an external serial clock synchronized with
LRCK.
External Serial Clock Mode
The CS4340 will enter the External Serial Clock Mode whenever 16 low to high transitions
are detected on the SCLK pin during any phase of the LRCK period.
The device will revert to Internal Serial Clock Mode if no low to high transitions are detected
on the SCLK pin for 2 consecutive periods of LRCK.
Clocks the individual bits of the serial data into the SDATA pin.
The required relationship between the Left/Right clock, serial clock and serial data is defined
by the DIF1-0 pins.
The CS4340 supports both internal and external serial clock generation modes.
Internal SCLK mode is used to gain access to extra de-emphasis modes.
Internal Serial Clock Mode
In the internal Serial Clock Mode, the serial clock is internally derived and synchronous with
the master clock and left/right clock.
The SCLK/LRCK frequency ratio is either 32, 48 or 64 depending upon the DIF1-0 pins.
Operation in this mode is identical to operation with an external serial clock synchronized with
LRCK.
External Serial Clock Mode
The CS4340 will enter the External Serial Clock Mode whenever 16 low to high transitions
are detected on the SCLK pin during any phase of the LRCK period.
The device will revert to Internal Serial Clock Mode if no low to high transitions are detected
on the SCLK pin for 2 consecutive periods of LRCK.
DEM1
Input
De-emphasis Control
Implementation of the standard 15
Implementation of the standard 15
µs/50 µs digital de-enphasis filter response, required
reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz
sample rates.
When using Internal Serial Clock Mode, as described above, Pin 3 is available for de-emphasis
control, DEM1, and all de-enphasis filters are available.
When using External Serial Clock Mode, as described above, Pin 3 is not available for
de-emphasis use and only the 44.1 kHz de-emphasis filter is available.
Note: De-emphasis is not available in High-Rate Mode.
sample rates.
When using Internal Serial Clock Mode, as described above, Pin 3 is available for de-emphasis
control, DEM1, and all de-enphasis filters are available.
When using External Serial Clock Mode, as described above, Pin 3 is not available for
de-emphasis use and only the 44.1 kHz de-emphasis filter is available.
Note: De-emphasis is not available in High-Rate Mode.
4
LRCK
Input
Left/Right Clock
The Left/Right clock determines which channel is currently being input on the serial audio
data input, SDATA. The frequency of the Left/Right clock must be at the input sample rate.
Audio samples in Left/Right sample pairs will be simultaneously output from the digital- to-
analog converter whereas Right/Left pairs will exhibit a one sample period difference.
The required relationship between the Left/Right clock, serial clock and serial data is defined
by the DIF1-0 pins.
The Left/Right clock determines which channel is currently being input on the serial audio
data input, SDATA. The frequency of the Left/Right clock must be at the input sample rate.
Audio samples in Left/Right sample pairs will be simultaneously output from the digital- to-
analog converter whereas Right/Left pairs will exhibit a one sample period difference.
The required relationship between the Left/Right clock, serial clock and serial data is defined
by the DIF1-0 pins.
5
MCLK
Input
Master Clock
The master clock frequency must be either 256x, 384x or 512x the input sample rate in Base
Rate Mode (BRM) and either 128x or 129x the input sample rate in High Rate Mode (HRM).
The master clock frequency must be either 256x, 384x or 512x the input sample rate in Base
Rate Mode (BRM) and either 128x or 129x the input sample rate in High Rate Mode (HRM).
Pin No.
Port Name
Input/Output
Function
Sample
Rate
(kHz)
MCLK (MHz)
HRM
BRM
128x
192x
256x
384x
512x
32
4.0960
6.1440
8.1920
12.2880
16.3840
44.1
5.6448
8.4672
11.2896
16.9344
22.5792
48
6.1440
9.2160
12.2880
18.4320
24.5760
64
8.1920
12.2880
88.2
11.2896
16.9344
96
12.2880
18.4320
Common Master Clock Frequencies
DEM1
DESCRIPTION
0
Disabled
0
44.1 kHz
1
48 kHz
1
32 kHz
Internal Serial Clock Mode
SD-EX220H
8 – 5
IC101 VHiCS4340KS-1: DAC IC (CS4340KS) (2/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal whitch is not connected to the outside.
Pin No.
Port Name
Input/Output
Function
6, 7
DIF1, DIF0
Input
Digital Interface Format
The required relationship between the Left/Right clock, serial clock and serial data is defined.
The required relationship between the Left/Right clock, serial clock and serial data is defined.
8
DEM0
Input
De-emphasis Control
Implementation of the standard 15
Implementation of the standard 15
µs/50 µs digital de-enphasis filter response, required
reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz
sample rates.
When using Internal Serial Clock Mode, as described above, Pin 3 is available for de-emphasis
control, DEM1, and all de-enphasis filters are available.
When using External Serial Clock Mode, as described above, Pin 3 is not available for
de-emphasis use and only the 44.1 kHz de-emphasis filter is available.
Note: De-emphasis is not available in High-Rate Mode.
sample rates.
When using Internal Serial Clock Mode, as described above, Pin 3 is available for de-emphasis
control, DEM1, and all de-enphasis filters are available.
When using External Serial Clock Mode, as described above, Pin 3 is not available for
de-emphasis use and only the 44.1 kHz de-emphasis filter is available.
Note: De-emphasis is not available in High-Rate Mode.
9
FILT+
Output
Positive Voltage Reference
Positive reference for internal sampling circuits.
An external capacitor is required from FILT+ to analog ground.
The recommended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 kHz.
FILT+ is not intended to supply external circuit. FILT+ has a typical source impedance of 250
kohms and any current drawn from this pin will alter device performance.
Positive reference for internal sampling circuits.
An external capacitor is required from FILT+ to analog ground.
The recommended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 kHz.
FILT+ is not intended to supply external circuit. FILT+ has a typical source impedance of 250
kohms and any current drawn from this pin will alter device performance.
10
VQ
Output
Quiescent Voltage
Filter connection for internal quiescent reference voltage, typically 50 % of VA.
Capacitors must be connected from VQ to analog ground.
VQ is not intended to supply external current.
VQ has a typical source impedance of 250 kohms and any current drawn from this pin will
alter device performance.
Filter connection for internal quiescent reference voltage, typically 50 % of VA.
Capacitors must be connected from VQ to analog ground.
VQ is not intended to supply external current.
VQ has a typical source impedance of 250 kohms and any current drawn from this pin will
alter device performance.
11
REF_GND
Input
Reference Ground
Ground reference for the internal sampling circuits. Must be connected to analog ground.
Ground reference for the internal sampling circuits. Must be connected to analog ground.
12
AOUTR
Output
Analog Output
The full scale analog output level is specified in the Analog Characteristics specifications table.
The full scale analog output level is specified in the Analog Characteristics specifications table.
13
AGND
Input
Ground
Ground Reference.
Ground Reference.
14
VA
Input
Analog Power
Analog power supply. Typically 3 to 5 VDC.
Analog power supply. Typically 3 to 5 VDC.
15
AOUTL
Output
Analog Output
The full scale analog output level is specified in the Analog Characteristics specifications table.
The full scale analog output level is specified in the Analog Characteristics specifications table.
16*
MUTEC
Output
Mute Control
The Mute Control pin goes high during power-up initialization, reset, muting, master clock to
left/right clock frequency ratio is incorrect or power-down this pin is intended to be used as a
control for an external mute circuit to prevent the clicks and pops that can occur in any single
supply system. Use of Mute Control is not mandatory but recommended for designs requiring
the absolute minimum in extraneous clicks and pops.
The Mute Control pin goes high during power-up initialization, reset, muting, master clock to
left/right clock frequency ratio is incorrect or power-down this pin is intended to be used as a
control for an external mute circuit to prevent the clicks and pops that can occur in any single
supply system. Use of Mute Control is not mandatory but recommended for designs requiring
the absolute minimum in extraneous clicks and pops.
DIF1
DIF0
DESCRIPTION
FORMAT
0
0
I
2
S, up to 24-bit data
0
0
1
Left Justified, 24-bit Data
1
1
0
Right Justified, 24-bit Data
2
1
1
Right Justified, 16-bit Data
3
Digital Interface Format
DEM0
DESCRIPTION
0
Disabled
1
44.1 kHz
External Serial Clock Mode
DEM0
DESCRIPTION
0
Disabled
1
44.1 kHz
0
48 kHz
1
32 kHz
Internal Serial Clock Mode
SD-EX220H
8 – 6
IC501 VHiLC75341M-1: Audio Processor (LC75341M)
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
17
LVref
RVref
CONTROL
CIRCUIT
CONTROL
CIRCUIT
CONTROL
CIRCUIT
LOUT
LBASS
LIN
LSEL0
L4
L3
L2
L1
R1 R2
R3
R4
RSEL0
RIN
RTRE
LTRE
RBASS
ROUT
VREF
VDD
CLK
DI
CE
VSS
CCB
INTERFACE
CD
Tuner
Tape
Video
24 23 22 21 20 19 18 17 16 15 14 13
1
2
3
4
5
6
7
8
9
10 11 12
LC75341M
DI
CE
VSS
LOUT
LBASS
LTRE
LIN
LSEL0
L4
L3
L2
L1
CLK
VDD
VREF
ROUT
RBASS
RTRB
RIN
RSEL0
R4
R3
R2
R1
SD-EX220H
8 – 7
IC701 RH-iX0557AWZZ: System Microcomputer (IX0557AW) (1/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal whitch is not connected to the outside.
Pin No.
Port Name
Terminal Name
Input/Output
Function
1
PA5/AN5
KEY2
A/D Input
A/D input, main set key.
2
PA4/AN4
KEY3
A/D Input
A/D input, main set key.
3
PA3/AN3
TUN_SM
Output
TUNER IF signal monitor.
4*
PA2/AN2
DAC_DATA
Output
Fix to "L".
5*
PA1/AN1
DAC_CLOCK
A/D Input
Digital analog converter CLK output.
6
PA0/AN0
PROTECT
A/D Input
Power abnormal detection.
7
P97/BUZ02/AN15
MOT_LOCK
A/D Input
Lid motor over current detection.
8
P96/PWM0/AN14
O/C_SW
A/D Input
A/D input, CD open/close switch.
9
P95/RTP0/AN13
H/P_SW
Input
Headphones switch input detection.
10
P94/RTP1/AN12
FAN_LOCK
A/D Input
Fan stop detection.
11
P93/SRDY3/AN11
FAN_CHK
Input
Ventilation fan motor control. H: FAN ON
12
P92/SCLK3/AN10
POWER_LEVEL 1
Input
1-bit amp. and power switch protect.
13
P91/SOUT3/AN9
POWER_LEVEL 2
Input
Speaker protect.
14
P90/SIN3/AN8
+B_CHK
Input
Observe power on input and decide reset timing.
15
P83/CNTR0/CNTR2
S_MUTE
Output
Audio mute control. H: MUTE ON
16
P82/CNTR1
TIMER_STBY
Output
Timer stand-by LED control. H: LED ON
17
CNVSS
CNVSS
Input
GND
18
RESET
RESET
Input
System microcomputer reset input. L: RESET
19
P81/XCOUT
SP_RELAY
Output
Speaker output control by relay. H: RELAY ON
20
P80/XCIN
POWER
Output
Main trans ON/OFF control by relay. H: RELAY ON
21
VSS
VSS
Input
GND
22
XIN
XIN
Input
Main clock input. 4.19 MHz
23
XOUT
XOUT
Output
Main clock input. 4.19 MHz
24
VCC
VCC
Input
Power supply 5 V.
25*
P77/INT4/BUZ01
NO USE
Output
Open.
26*
P76/T3OUT
CD_FUNC
Output
CD & Ext. DIG function selector.
27
P75/T1OUT
DIG_FUNC
Output
Ext. DIG out ON/OFF control.
L: DIG OUT ON, H: DIG OUT OFF
L: DIG OUT ON, H: DIG OUT OFF
28
P74/PWM1
A/D_RESET
Output
1-bit amp. A/D reset control.
29*
P73/INT3/DIMOUT
NO USE
Output
Open.
30
P72/INT2
RX-IN
Input
Remote control decoder input.
31
P71/INT1
SYS_STOP
Input
AC power signal monitor.
32
P70/INT0
OFFSET
Input
1-bit amp. offset error detection.
33
P67/SRDY2/SCLK/FLD55
CD_RESET
Output
SANYO CD DSP reset output. L: RESET
34
P66/SCLK2/FLD54
CD_CLK
Output
SANYO CD DSP interface clock output.
35
P65/TXD/FLD53
CD_DI
Output
SANYO CD DSP interface data output.
36
P64/RXD/FLD52
CD_CE
Input
SANYO CD DSP interface chip enable.
37
P63/FLD51
CD_DO
Input
SANYO CD DSP interface data input.
38
P62/FLD50
CD_DRF
Input
SANYO CD DSP RF monitor signal.
39
P61/FLD49
CD_WRQ
Input
SANYO CD DSP interface syncro signal.
40
P60/FLD48
CE
Output
SANYO TUNER PLL/VOL IC interface chip enable output.
41
P57/FLD47
CLK
Output
SANYO TUNER PLL/VOL IC interface clock output.
42
P56/FLD46
DI
Output
SANYO TUNER PLL/VOL IC interface data output.
43
P55/FLD45
DO
Input
SANYO TUNER PLL/VOL IC interface data input.
44
P54/FLD44
EQ_CONT
Output
VOL 0-26: H, VOL 27-40: L
POWER OFF, CLOCK CONFIRMATION: L
POWER OFF, CLOCK CONFIRMATION: L
45
P53/FLD43
40V_RELAY
Output
40 V control port. "H": ACTIVE, "L": OFF
46*-48*
P52/FLD42-P50/FLD40
NO USE
Output
Open.
49*-55*
P47/FLD39-P41/FLD33
NO USE
Output
Open.
56
P40/FLD32
SEG_24
Output
FL segment driver.
57-64
P37/FLD31-P30/FLD24
SEG_23-SEG_16
Output
FL segment driver.
65-72
P17/FLD23-P10/FLD16
SEG_15-SEG_8
Output
FL segment driver.
73-79
P07/FLD15-P01/FLD9
SEG_7-SEG_1
Output
FL segment driver.
80
P00/FLD8
DIG_9
Output
FL digit driver.
81-88
P27/FLD7-P20/FLD0
DIG_8-DIG1
Output
FL digit driver.
89
VEE
VEE
Input
VLOAD -35 V.
90
PB6/SIN1
RDS_RST
Output
RDS RAM reset.
91
PB5/SOUT1
RDS_DATA
Input
RDS data input.
92
PB4/SCLK11
RDS_CLK
Output
RDS clock output.
93
PB3/SSTB1
RDS_RDY
Input
RDS ready output.
94*
PB2/SBUSY1
—
Output
Connect to ground.
95
PB1/SRDY1
SURROUND
Output
Surround output control.
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