Sharp SD-EX100H (serv.man21) Service Manual ▷ View online
– 69 –
SD-EX100H
IC701 VHiTA2157F/-1: Head AMP. (TA2157F)
94k
Ω
22k
Ω
15pF
240k
Ω
94k
Ω
22k
Ω
40pF
40pF
180k
Ω
180k
Ω
60k
Ω
60k
Ω
3k
Ω
3k
Ω
20k
Ω
20k
Ω
20k
Ω
40k
Ω
40k
Ω
10pF
15pF
13
GVSW
18
RFRPIN
19
RFGO
RFGC
20
21
AGCIN
22
RFO
23
RFN
24
GND
12
RFDC
11
TEO
10
TEN
9
TEBC
8
SEL
7
LDO
6
MDI
5
TNI
4
TPI
3
FPI
2
FNI
1
VCC
20k
Ω
20k
Ω
15k
Ω
2k
Ω
1.75k
Ω
14k
Ω
1k
Ω
50k
Ω
2k
Ω
1.3V
20k
Ω
12k
Ω
12k
Ω
20k
Ω
40k
Ω
50k
Ω
15k
Ω
30k
Ω
20k
Ω
240k
Ω
10pF
14
VRO
15
FEO
16
FEN
17
RFRP
BOTTOM
PEAK
PEAK
x0.5
x2
K
x0.5
x2
1
50uA
40uA
1
VCC
—
3.3V power supply terminal
2
FNI
Input
Main beam amp input terminal
3
FPI
Input
Main beam amp input terminal
4
TPI
Input
Sub-beam amp input terminal
5
TNI
Input
Sub-beam amp input terminal
6
MDI
Input
Monitor photodiode amplifier input terminal
7
LDO
Output
Laser diode amp output terminal
8
SEL
Input
APC circuit ON/OFF signal, LDO terminal control input terminal and bottom/peak
detection frequency switching terminal
detection frequency switching terminal
9
TEBC
Input
Tracking error balance adjustment signal input terminal
• TEBC input voltage
• TEBC input voltage
10
TEN
Input
Tracking error signal generation amp antiphase input terminal
11
TEO
Output
Tracking error signal generation amp output terminal
12
RFDC
Output
RF signal peak detection output terminal
13
GVSW
Input
AGC, FE, TE amp gain switching terminal
14
VRO
Output
Reference voltage (VRO) output terminal • VCC=3.3V: VRO=1/2 VCC
15
FEO
Output
Focus error signal generation amp output terminal
16
FEN
Input
Focus error signal generation amp antiphase input terminal
17
RFRP
Output
Signal generation amp output terminal for track count
18
RFRPIN
Input
Signal generation amp input terminal for track count
19
RFGO
Output
RF signal amplitude adjustment amp output terminal
20
RFGC
Input
RF amplitude adjustment control signal input terminal • RFGC input voltage
21
AGCIN
Input
RF signal amplitude adjustment amp input terminal
22
RFO
Output
RF signal generation amp output terminal
23
RFN
Input
RF signal generation amp input terminal
24
GND
—
GND terminal
Terminal Name
Pin No.
Input/Output
Function
GND
OFF
Connection to VCC via 1k
Ω
Hi-z
ON
Control signal output
VCC
ON
Control signal output
SEL
APC circuit
LDO
GND
CD-RW
Hi-z
CD-DA
VCC
CD-CA
GVSW
Mode
Figure 69 BLOCK DIAGRAM OF IC
SD-EX100H
– 70 –
IC702 VHiTC94A14F-1: Servo/Signal Control (TC94A14F) (1/2)
1
BCK
Output
Bit clock output terminal
At constant speed:
3-5I/F
32 fs, 48 fs and 64 fs selectable according to commands
32 fs = 1.4112 MHz
2
LRCK
Output
LR Channel clock output terminal. "L" for Channel L, "H" for Channel R.
At constant speed:
3-5I/F
Output polarity invertible by command
44.1kHz
3
AOUT
Output
Audio data output terminal.
3-5I/F
MSB/LSB First selectable by command
4
DOUT
Output
Digital-out output terminal.
In accordance with
3-5I/F
Output up to double speed possible
CP-1201
5*
IPF
Output
Correction flag output terminal
Also known as
3-5I/F
When AOUT output in C2 correction output is uncorrectable symbol: "H"
“C2PO”
6
VDD3
Input
Digital 3.3 V power supply terminal
7
VSS3
—
Digital GND terminal
8
SBOK
Output
Output terminal for CRCC judgment result of Sub Code Data Q
3-5I/F
When judgment result is OK: "H"
9*
CLCK
Input/Output
Clock input-output terminal for reading Sub-code P – W data
On entry: Schmitt
3-5I/F
Input/Output polarity selectable by command
10*
DATA
Output
Sub-code P – W data output terminal
3-5I/F
11*
SFSY
Output
Regenerative frame sink signal output terminal
3-5I/F
12*
SBSY
Output
Sub-code block sink output terminal
3-5I/F
When sub-code sink is detected: "H" at the position of S1
13
IO0
Input/Output
General propose input-output terminal. Input port during reset.
On entry: Schmitt
3-5I/F
14*
IO1
Input/Output
3-5I/F
15
PVDD3
Input
3.3 V Terminal exclusively for PLL system
16
PDO
Output
Output terminal for phase error signal of signals EFM and PLCK
Four-valued output
AI/F
(PVDD3,HiZ,PVREF,AVSS3)
17
TMAX
Output
TMAX Detection result output terminal
Three-valued output
AI/F
(PVDD3,HiZ,AVSS3)
18
LPFN
Input
Inverting input terminal of amplifier for PLL low pass filter
Analog input
AI/F
19
LPFO
Output
Output terminal of amplifier for PLL low pass filter
Analog output
AI/F
20
PVREF
—
VREF Terminal exclusively for PLL
21
VCOF
Output
Filter terminal for VCO
Analog output
AI/F
22
AVSS3
—
Analog GND terminal
23
SLCO
Output
DAC Output terminal for producing data slice level
Analog output
AI/F
24
RFI
Input
RF Signal input terminal. Zin selectable by command.
Analog input
AI/F
25
AVDD3
Input
Analog 3.3 V power supply terminal
26
RFCT
Input
RFRP Signal center level input terminal
Analog input
AI/F
Zin = 33k
Ω
27
RFZI
Input
RFRP Signal zerocross input terminal
Analog input
AI/F
28
RFRP
Input
RF Ripple signal input terminal
Analog input
AI/F
29
FEI
Input
Focus error signal input terminal
Analog input
AI/F
30
SBAD
Input
Sub beam counting signal input terminal
Analog input
AI/F
Terminal
Name
Input/
Output
Function
Remarks
Terminal
No.
TMAX Detection result
TMAX Output
"PVDD3"
"HiZ"
"AVSS3"
Longer than the specified period
Within the specified period
Shorter than the specified period
In this unit, the terminal with asterisk mark (*) is open terminal which is not connected to the outside.
– 71 –
SD-EX100H
IC702 VHiTC94A14F-1: Servo/Signal Control (TC94A14F) (2/2)
31
TEI
Input
Tracking error input terminal
Analog input
AI/F
Import during tracking servo on
32
TEZI
Input
Input terminal for tracking error signal zerocross
Analog input
AI/F
Zin = 10k
Ω
33
FOO
Output
Focus equalizer output terminal
Analog output
AI/F
(AVSS3~AVDD3)
34
TRO
Output
Tracking equalizer output terminal
AI/F
35
VREF
Input
Analog reference power supply terminal
36
RFGC
Output
RF Amplitude adjusting control signal output terminal
Three-valued output
AI/F
(PWM carrier=88.2kHz)
37
TEBC
Output
Tracking balance control signal output terminal
(AVDD3,VREF,AVSS3)
AI/F
38
SEL
Output
APC Circuit ON/OFF signal output terminal. When laser is ON;
Three-valued output
AI/F
"HiZ" output in case of UHS = "L"; "H" output in case of UHS = "H"
39
AVDD3
Input
Analog 3.3 V power supply terminal
40
FMO
Output
Feed equalizer output terminal
Three-valued output
AI/F
(PWM carrier=88.2kHz)
41
DMO
Output
Disc equalizer output terminal
(AVDD3,VREF,AVSS3)
AI/F
42
VSS3
—
Digital GND terminal
43
VDD3
Input
Digital 3.3 V power supply terminal
44
TESIN
Input
Test input terminal. Normally fixed at "L"
3I/F
45
XVSS3
—
GND Terminal for system clock oscillating circuit
46
XI
Input
System clock oscillating circuit input terminal
AI/F
47
XO
Output
System clock oscillating circuit output terminal
AI/F
48
XVDD3
Input
3.3 V power supply terminal for system clock oscillating circuit
49
DVSS3
—
GND Terminal for DA converter
50*
RO
Output
R Channel data normal rotation output terminal
AI/F
51
DVDD3
Input
3.3 V power supply terminal for DA converter
52
DVR
—
Reference voltage terminal
53*
LO
Output
L Channel data normal rotation output terminal
AI/F
54
DVSS3
—
GND Terminal for DA converter
55*
ZDET
Output
1-Bit DA converter 0-detection flag output terminal
3-5I/F
56
VSS5
—
GND Terminal for microcomputer interface
57
BUS0
Input/Output
Data Input-output terminal for microcomputer interface
Schmitt input
58
BUS1
3-5I/F
CMOS port
59
BUS2
60
BUS3
61
BUCK
Input
Clock input terminal for microcomputer interface
Schmitt input
3-5I/F
62
/CCE
Input
Chip enable signal input terminal for microcomputer interface.
Schmitt input
3-5I/F
BUS0 – 3 active in case of "L".
63
/RST
Input
Reset signal input terminal. "L" during reset.
Built-in pull-up resistor
3-5I/F
64
VDD5
Input
5 V power supply terminal for microcomputer interface
Terminal
Name
Input/
Output
Function
Remarks
Terminal
No.
Note: AI/F: Analog input-output terminal
3-5I/F: Built-in 3-5 interface terminal (5 V input-output terminal)
3I/F: 3V input-output terminal
3I/F: 3V input-output terminal
In this unit, the terminal with asterisk mark (*) is open terminal which is not connected to the outside.
SD-EX100H
– 72 –
Figure 72 BLOCK DIAGRAM OF IC
IC704 VHiLA6558++-1: Focus/Tracking/Spin/Sled/Loading Driver (LA6558)
Thermal shutdown
MUTE(input ON/OFF)
15.4k
15.4k
11k
11k
VCC
MUTE
VIN1
VG1
VO1+
VO1–
GND
GND
GND
VO2–
VO2+
VG2
VIN2
REG-OUT
REG-IN
VCC
VREF
VIN4
VG4
VO4+
VO4–
GND
GND
GND
VO3–
VO3+
VG3
VIN3
CD
RESET
11k
11k
15.4k
15.4k
Level shift
Level shift
Level shift
Level shift
3.3VREG
Reset
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
VCC
Power (short-circuited to pin 30).
2
MUTE
All CH output ON/OFF.
3
VIN1
CH1 input terminal.
4
VG1
CH1 input terminal. (for gain adjustment)
5
VO1+
CH1 output terminal. (noninversion side)
6
VO1–
CH1 output terminal. (inversion side)
7-9
GND
GND terminal
10
VO2–
CH2 output terminal. (inversion side)
11
VO2+
CH2 output terminal. (noninversion side)
12
VG2
CH2 input terminal. (for gain adjustment)
13
VIN2
CH2 input terminal.
14
REG-OUT
Connect the collector of externally provided transistor (PNP). 3.3VREG power output.
15
REG-IN
Connect the base of externally provided transistor (PNP).
16
RESET
Reset output.
17
CD
Reset output delay time setting. (capacitor provided externally)
18
VIN3
CH3 input terminal.
19
VG3
CH3 input terminal. (for gain adjustment)
20
VO3+
CH3 output terminal. (noninversion side)
21
VO3–
CH3 output terminal. (inversion side)
22-24
GND
GND terminal
25
VO4–
CH4 output terminal. (inversion side)
26
VO4+
CH4 output terminal. (noninversion side)
27
VG4
CH4 input terminal. (for gain adjustment)
28
VIN4
CH4 input terminal.
29
VREF
Application of standard voltage of level shift circuit.
30
VCC
Power (short-circuited to pin 1).
Pin
No.
No.
Function
Terminal Name
GND (lowest potential) is connected to pins 7-9 and pins 22-24.
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