Sharp SD-AT100 (serv.man3) Service Manual ▷ View online
SD-AT100H
– 44 –
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
9
37
1
2
3
1
2
3
8
7
6
5
4
3
2
1
33
32
31
30
29
28
27
26
25
24
23
11
10
9
8
7
6
5
4
3
2
1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
39
39
38
37
36
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32
31
30
29
29
17
16
15
14
13
12
11
10
9
8
7
7
6 5 4 3 2 1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
28
44 43 42 41 40 39 38 37 36 35 34
14 15 16 17 18 19 20 21 22
12 13
/EXTMEM
_DSP_INTREQ
_DSP_SCDOUT
_DSP_CS
EMAD0
EMAD1
EMAD2
EMAD3
EMAD4
EMAD5
EMAD6
EMAD7
_DSP_SCCLK
_DSP_SCDIN
/EMOE
/EMWR
LRCK
W_SP_RLY
EX_CLK
DSP_RESET
SCLK
LRCK
SCLK
SDATA1
SDATA1
_DSP_SCDOUT
_DSP_CS
_DSP_SCDIN
SCL
ROM
DSP_UC16
DSP_RESET
DSP_UC15
SDA
W_SP_RLY
DSP_UC17
DIG_FUNC+B
SPDIF
DSP_SCDIN
DSP_SCDOUT
DSP_INTREQ
DSP_ABOOT
DSP_SCCLK
PROTECT
_DSP_SCCLK
_DSP_INTREQ
SCL
SDA
AUDATA2
AUDATA1
LRCK
SDATA1
MCLK
AUDATA0
SCLK
EX_CLK
DSP_CS
LRCK
SCLK
MCLK
AUDATA1
AUDATA0
PVDD
R
PVSS
RX4
SLAVE
RX3
TST
RX2
I2C
RX1
CAD0/CSN
SCL/CCLK
SDA/CDTI
CAD1/CDTO
INT1
INT0
MCKO
TX
XTI/EXTCLK
XTO
SCLKN2
LRCLKN2
LRCLKN2
SDATAN2
SCCLK
SCDIN
SCDOUT
CS
INTREQ
EXTMEM
SDATAN1
SCLKN1
LRCLKN1
D0
D1
D2
D3
D4
D5
D6
D7
RD
WR
XMT958
MCLK
SCLK
LRCLK
AUDATA0
AUDATA1
AUDATA2
CLKIN
CLKSEL
FILT2
FILT1
RESET
DD
DC
AGND
VA
DGND3
DGND2
DGND1
VD3
VD2
VD1
DZF2/OVF
VCOM
VREFH
AVDD
AVSS
DZF1
LIN
RIN
ROUT1
ROUT2
ROUT3
LOUT3
LOUT2
LOUT1
PDN
DVSS
DVDD
TVDD
SDTO
SDTI3
SDTI2
SDTI1
LRCK
BICK
+
+
–
–
VSS
VDD
VCC
GND
TO DSP PWB (2/2)
D_+2.5V
IC101
74HC07AF
BUFFER AMP.
IC103
GP1F38R
OPTICAL FIBER
DATA LINK
Q101
IC104
GP1F38T
OPTICAL FIBER
DATA LINK
IC102
AK4586VQ
ADC/DAC/DIR
CONVERTER
IC105
CS493292
DSP
IC106
NJM4580M
OPE AMP.
OPE AMP.
Q104
Q103
Q102
Figure 44 BLOCK DIAGRAM (7/17)
– 45 –
SD-AT100H
15
17
19
38
14
39
3 1
8
7
6
5
14
13
12
11
10
9
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
3 1
8
7
6
5
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
39
38
37
36
35
34
33
32
31
30
29
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2
2
LRCK
W_SP_RLY
EX_CLK
R_IN
L_IN
A_–12V
A_+12V
R_OUT
L_OUT
SW_OUT
C_OUT
SR_OUT
SL_OUT
/EMWR
DSP_RESET
A_+5V
A_+2.5V
D_+3.3V
EX_CLK
D_+5V
/ROM
ROM
AUDATA2
EMAD3
EMAD2
EMAD1
EMAD0
EMAD7
EMAD6
EMAD5
EMAD4
A15
DSP_UC16
EMAD0
EMAD1
EMAD2
EMAD3
EMAD4
EMAD5
EMAD6
EMAD7
/EXTMEM
A10
A3
A2
A1
A0
A4
A5
A6
A7
A12
A14
A13
A8
A9
A11
EMAD4
EMAD0
EMAD5
EMAD1
EMAD6
EMAD2
EMAD7
EMAD3
/EXTMEM
A2
A0
A1
A3
A10
A14
DSP_UC16
A8
A11
A13
DSP_UC15
A12
A9
A5
A4
A6
DSP_UC17
A7
/EMOE
A2
A1
A0
A7
A6
A5
A4
A3
A15
A14
A13
A12
A11
A10
A9
A8
A3
A0
A4
A1
A5
A2
A6
A7
/EMOE
VDD
I/O8
VSS
1A
1Y
2A
2Y
3A
3Y
GND
VCC
O/I4
O/I3
O/I2
O/I1
I/O1
I/O2
I/O3
I/O4
FROM MAIN PWB
VDD
VSS
CONT3
CONT2
CONT4
CONT1
D3
D7
Q6
Q4
Q2
D1
VCC
OE
D6
D2
D5
D0
CK
Q7
Q3
Q0
Q1
Q5
GND
D4
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CK
GND
D7
D6
D5
D4
D3
D2
D1
D0
OE
O7
O6
O5
O4
O3
O2
O1
O0
GND
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
WE
CE
CE2
CE1
OE
OE
PGM
VPP
VCC
A17
A16
A16
A15
A15
A14
A14
A13
A13
A12
A12
A11
A11
A10
A10
A9
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
NC
KIN
SEL
LT2
LT1
SET
DD
DC
ND
VA
5
6
7
8
4
1
3
2
9
10
11
12
13
14
15
VDD
VSS
+
+
–
–
+
VDD
+
VSS
–
–
TO MAIN PWB (1/2)
TO DSP PWB (2/2)
CNS101
+B
M
P.
IC110
BU4066BCF
ANALOG SWITCH
IC108
NJM4580M
OPE AMP.
IC109
NJM4580M
OPE AMP.
R148
10K
IC116
T15N1055
SRAM
IC117
MX27L212
EPROM
Q105
IC112
IX0446AW
VOLTAGE REGULATOR
IC111
IX0446AW
VOLTAGE REGULATOR
IC115
TVHC574T
LATCH
Q104
Q103
Q102
X101
12.288 MHz
IC107
TC7WU04U
DUAL2-INPUT
NAND GATE
CNP101
IC114
TVHC574T
LATCH
Figure 45 BLOCK DIAGRAM (8/17)
SD-AT100H
– 46 –
ROM DOWNLOAD
PLUG
1
2
3
4
5
6
7
8
9 10 11 12
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
+3.3V(SWD)
POSISTOR
OFFSET
DVD_CLK
DVD_WRITE
DVD_KDATA
DVD_DATA
DVD_STB
POSISTOR
A/D_RESET
POWER
CNS301
TO DISPLAY PWB
F_CONT
FLD_CS
FLD_SDATA
FLD_SCK
FLD_RESET
TIMER_LED
DD_LED
DPL_LED
STD_LED
DTS_LED
VIR_LED
AAC_LED
KEY2
KEY1
RX_IN
POWER_KEY
DVD_+B
PROTECT
KEY1
C_SP_RLY
F_SP_RLY
POWER_KEY
TU_MUTE
CCB_CE
CCB_CL
SD_ST_IN
CCB_DI
AREA
DOOR_PROT
PROTECT
CCB_DO
TV_TYPE
TUNER_SM
SDA
SCL
FLASH_VCC
RESET
DVD_STB
DVD_KDATA
DVD_CLK
DVD_WRITE
DVD_DATA
FLD_RESET
FLD_SDATA
FLD_SCK
FLD_CS
DPL_LED
AAC_LED
SYS_STOP
RX_IN
VIR_LED
DTS_LED
STD_LED
DD_LED
TIMER_LED
ROM
DSP_ABOOT
_A/D_RESET
DOOR_M–
DOOR_M+
A/D_RE_MONI
VOL_DATA
VOL_STB
VOL_CLK
DVD_+B
BASS_SW
_S_MUTE
DIG_FUNC+B
POWER
S_SP_RLY
-B_CONT
W_SP_RLY
FAN_MOTOR
H.P_SW
DSP_INTREQ
DOOR_CL
DOOR_OP
DOOR_SPED
S_MUTE
A/D_RESET
+3.3V(USWD)
+3.3V(SWD)
V_SEL4
V_SEL3
V_SEL2
V_SEL1
KEY2
P96
P95
P94
P93
P92
P91
P90
CNVSS
P87
P86
RESET
XOUT
P84
VSS
XIN
VCC
P85
P83
P
P
P
P
P42
P41
P40
P37
P36
P35
P34
P33
P32
P31
VCC
P30
VSS
P27
P43
P26
P25
P24
P23
P22
P21
P20
P17
P16
P15
P14
P13
P12
P11
P10
P07
P06
P05
P04
P03
P02
P01
P00
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AVSS
AN0
VREF
AVCC
P97
BYTE
P82
P81
P80
P77
P76
P75
P74
P73
P72
P71
P70
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
9
10
11
12
13
14
15
16
17
18
19
20
21
22
22
5
7
8
6
1
1
3
4
2
TO
DVD SERVO PWB
7
8
9 10 11 12
12
6
4
3
1
1
2
5
1
2
+B
CNP301
Q306
Q301
IC301
IX0489AW
SYSTEM MICROCOMPUTER
X301
8.38 MHz
CNP308
CNP302
CP3202
74
G
Figure 46 BLOCK DIAGRAM (9/17)
– 47 –
SD-AT100H
M
3
1
3
1
5
4
2
23 24 25 26 27 28 29 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
2
1
3
2
9
10
11
12
13
14
8
1
2
3
4
5
6
7
2
3
6
8 10
15
13
11
12 14 16
9
1
4
5
7
POSISTOR
DOOR_M+
DOOR_M–
A_+12V
A_–12V
+3.7V_STAND-BY
TO DISPLAY
PWB
P
V-MODE
V_SEL4
V_SEL3
ASPECT
L_MUTE
W_SP_RLY
TU_MUTE
C_SP_RLY
TUNER_SM
S_SP_RLY
F_SP_RLY
SD_ST_IN
CCB_CE
CCB_CL
CCB_DO
CCB_DI
–B_CONT
OFFSET
BASS_SW
S_MUTE
PROTECT
VOL_DATA
VOL_STB
VOL_CLK
FAN_MOTOR
H.P_SW
FM_STB
V_SEL1
V_SEL2
F_CONT
FLASH_EPM
DSP_UC16
DSP_CS
L_MUTE
DSP_SCDIN
DSP_UC15
DSP_UC17
DSP_SCCLK
DSP_SCDOUT
DSP_RESET
AUDITION
FM_STB
V-MODE
ASPECT
FLASH_CE
SDA
SCL
FLASH_BUSY
FLASH_TXD
FLASH_RXD
FLASH_SCLK
DPL_LED
AAC_LED
VIR_LED
DTS_LED
STD
_
LED
SDA
SCL
DSP_CS
DSP_RESET
DSP_SCCLK
DSP_SCDOUT
DSP_SCDIN
+9V_RELAY
D_5V
M+
M–
DOOR_OP
DOOR_CL
DSP_UC17
DSP_UC16
DSP_UC15
ROM
DSP_ABOOT
M+
M–
D_M–
D_M+
DOOR_PROT
+3R3V(SWD)
SPDIF
W_SP_RLY
DSP_INTREQ
DIG_FUNC+B
PROTECT
PROTECT
VOL_DATA
VOL_STB
VOL_CLK
DOOR
_
SPED
RESET SYS_STOP
SYS_STOP
+3.3V(USWD)
+3.3V(BACK_UP)
V_SEL4
V_SEL3
V_SEL2
V_SEL1
FLASH_VCC
RESET
FLASH_SCLK
FLASH_RXD
FLASH_TXD
FLASH_BUSY
AUDITION MODEL:HI
TO MAIN PWB
P67
P46
P45
P44
P42
P41
P40
P37
P36
P35
P34
P43
P77
P76
P75
P74
P73
P72
P71
P70
P66
P65
P64
P63
P62
P61
P60
P57
P56
P55
P54
P53
P52
P51
P50
P47
RESET
POINT
1
2
3
1
2
3
2
9
8
7
6
5
4
3
1
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
32
5
4
6
2
3
22
37
25
30
24
29
34
33
32
31
28
23
26
27
36
35
18
39
38
9
1
1
2
1
2
1
8
7
6
9
4
5
3
2
1
O PWB
12
VCC
GND
CNS306
TO
DSP PWB (1/2)
+B
+B
+B
CNP302
Q303
Q302
IC303
PST9127N
RESET
IC306
IX0445AW
VOLTAGE
VOLTAGE
REGULATOR
IC305
NJM7805D
VOLTAGE
REGULATOR
CNP305
IC304
74VHCT08
GATE IC
Q304
IC302
TA7291F
MOTOR DRIVER
CNP307
CNP303
CNS303
CNP304
CNS304
SW1
OPEN/CLOSE
M3
DVD/CD LID
MOTOR
CNP306
CNSE03
Figure 47 BLOCK DIAGRAM (10/17)
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