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QT-V5E/QT-V5H

5 – 17

B R

COLOR TABLE

R D ( R )

O R

Y L

G R

B L

V L

G Y

W H ( W )

B K

P K

BROWN

RED

ORANGE

YELLOW

GREEN

BLUE

VIOLET

GRAY

WHITE

BLACK

PINK

1

1

5

5

4

3
2
1

1

1

2

3

3

2

1

3

4

1

2

3

4

4

4

3

2

1

RD

BK

BK

WH

RD BK BK WH

BK

RD

WH

BK

R-CH

SPEAKERS

SP1,2

L-CH

SPEAKERS

CN204

P5-15 4-D

TO

AMP. PWB

BR

OR

YL

GR

RD

OR

YL

GR

CN05A

P5-13 1-F

TO

DVD SERVO PWB

CN4

P5-18 4-F

TO

TUNER PWB

CN01

1

1

1

1

2

2

1

2

1

2

CN206

BK

RD

P5-15 2-H

TO

AMP.PWB

9

9

CN202

P5-15 4-F

TO

AMP.PWB

BATTERIES
DC 12 V [ "D" size
(UM/SUM-3,R6AA)

battery x 2 ]

IC301

1

5

10

15

20

21

25

30

35 45

50

55

60

65

70

75

80

61

40

41

DISPLAY-E

SWITCH-D

SW508

OPEN/CLOSE

CN501

SW507

TUNER(BAND)

SW506 SKIP

PU

SW505

SKIP

DOWN

SW504 PLA

Y

SW503 ST

OP

SW502

VOLUME

UP

SW501

VOLUME

DOWN

6

1

1

6

1

2

3

4

5

6

D317

R355

C323

C322

C321

C320

C319

C318

QT-V5E/QT-V5H

5 – 18

1 2 3 4 5

CN05A

P5-17 6-C

FROM

DISPLAY PWB

CN208

P5-15 1-D

FROM

AMP. PWB

ROD

ANTENNA(244)

TUNER PWB-C

1
2

3

4

5

6

7

8

9

10

11
12

14

13

16

15

18

17

20

19

22

21

24

23

IC103

L100

AM BAR ANTENNA

1

9

10

18

5

15

IC101

QT-V5E/QT-V5H

6 – 1

Audio

QT-V5E/QT-V5H

Service Manual

QT-V5E/QT-V5H

Market

E

 

1

XOUT

OUTPUT

Crystal oscillation

For generation of standard frequency and internal clock. Connected to 7.2 MHz 
crystal resonator.

2

XIN

INPUT

Crystal oscillation

3

CE

INPUT

Chip enable

When CE is H, DA is synchronous with the rise of CK and read to the internal 
shift register. DA is then latched at the timing of the fall of CE. Also, output data 
is output from the CD terminal synchronous to the rise.

4

DA

INPUT

Serial data 

5

CK

INPUT

Clock signal

6

DO

——

Data out

Comes ON during IF frequency detection or SD detection.

7

SD

INPUT

SD input

SD signal is input, Observed by DO terminal. Input is for IF frequency.

8

IFIN

INPUT

IF input

9

P3

——

OUTPUT

Controlled on the basis of input.

10

P0

——

11

P1

——

12

P2

——

13

AMIN

INPUT

AM input

Local input for AM.

14

FMIN

INPUT

FM input

Local input for AM.

15

VDD

INPUT

Power supply

Power supply, with 4.0 V to 6.0 V applied voltage.

16

PD1

——

Phase compari-
son output

High level when value obtained by dividing local output is higher than standard 
frequency. Low level when value is lower. High impedance when value is same.

17

PD2

——

18

VSS

——

GROUND

GROUND

1

GND

Ground pin.

2

FB2

Inverting inputs to the error amplifiers. These pins work as feedback inputs for each channel, and are connected 
directly to the output of the switching regulator via a resistor divider to set the output voltages.

3

COMP1

Compensation pins for the error amplifiers.

4

COMP2

Compensation pins for the error amplifiers.

5

VCH2

Supply voltage for the high side output drivers. These are connected to voltages that must be at least 4 v higher than 
their bus voltages (assuming 5 v threshold MOSFET). A minimum of 1

µF high frequency capacitor must be con-

nected from these pins to PGng pin to provide peak drive current capability.

6

HDRV2

Output driver for the high side power MOSFET. Connect a diode, such as BAT54 or 1N4148, from these pins to 
ground for the application when the inductor current goes negative (Source/Sink), soft-start at no load and for the 
fast load transient from full load to no load.

7

LDRV2

Output driver for the synchronous power MOSFET.

8

PGND

This pin serves as the separate ground for MOSFET’s driver and should be connected to the system’s ground plane.

9

VCC

Supply voltage for the internal blocks of the IC.

10

LDRV1

Output driver for the synchronous power MOSFET.

11

HDRV1

Output driver for the high side power MOSFET. Connect a diode, such as BAT54 or 1N4148, from these pins to 
ground for the application when the inductor current goes negative (Source/Sink), soft-start at no load and for the 
fast load transient from full load to no load.

12

VCH1

Supply voltage for the high side output drivers. These are connected to voltages that must be at least 4 v higher than 
their bus voltages (assuming 5 v threshold MOSFET). A minimum of 1

µF high frequency capacitor must be con-

nected from these pins to PGng pin to provide peak drive current capability.

13

VOUT3

Driver signal for the LDO’s external transistor.

14

FB3

LDO’s feedback pin, connected to a resistor divider to set the output voltage of LDO.

15

SS

Soft-Start pin. THE converter can be shutdown by pulling this pin below 0.5 v.

16

FB1

Inverting inputs to the error amplifiers. These pins work as feedback inputs for each channel, and are connected 
directly to the output of the switching regulator via a resistor divider to set the output voltages.

QT-V5E/QT-V5H

6 – 2

Bias

Generator

LDrv2

Two Phase

Oscillator

1.25V

3V

Ramp1

Fb3

0.5V

POR

POR

Gnd

HDrv2

VcH2

SS

Comp2

Error Amp2

PWM Comp2

POR

V

OUT3

25uA

Reset Dom

LDrv1

HDrv1

VcH1

Fb1

Comp1

Error Amp1

PWM Comp1

25K

25K

Reset Dom

Set1

Set2

Ramp2

64uA Max

UVLO

VcH2

3.5V / 3.3V

VcH1

3.5V / 3.3V

4.2V / 4.0V

Fb2

25K

40mA LDO Controller

PGnd

Vcc

1.25V

1.25V

SS > 2V

R

S

Q

S

R

Q

Vcc

9

15

16

3

2

4

14

1

12

11

10

5

6

7

8

13

1.25V

2V

SS

25K

25K

25K